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UCC27611: Rise and Fall Time

Ben Alsin
Prodigy 60 points

Part Number: UCC27611
Other Parts Discussed in Thread: CSD17313Q2

Hi,

I am using the UCC27611 to drive a GaN Fet (EPC2204). The rise and fall times in my current design do not match what is in the datasheet.

 

I do get 5ns fall times, however, the rise times are around 20ns. I need <10ns rise times for my application to work correctly. I have tried reducing the gate resistors down to 0 ohm, but unfortunately 20ns rise times is still the best I am seeing.

I am powering the UCC27611 with 5V VDD. I have a suspicion this might be the issue causing the slow rise times. The datasheet seems to use VDD 12V for most of the specs listed. Does VDD have an impact on rise and fall times? Is there a graph or any extra data available for the UCC27611 detailing VDD vs rise/fall times? 

I want to verify raising VDD to 12V or higher will reduce the rise time down to <10ns before I redesign the circuit.

Thanks!

  • 0
    TI__Genius 11810 points

    Hi Ben,

    For many of our drivers, the rise and fall time heavily depends on VDD. For this one, the driver stage is powered by Vref, which should be a steady 5V over the valid VDD range. Therefore, it likely won't vary much based on VDD. Do you have a scope capture of the output waveform? That will make it easier to determine the root cause. One thing that can be challenging, is that the turn-on loop is much larger than the turn-off loop:

    Green is turn-off and Red is turn-on. Therefore, the layout of the Vref circuit needs to be low-inductance or the rise time will be longer. The internal impedance of the Vref capacitor can play a large role. In addition, scope measurements can make the rise time look longer if there is GND lifting/inductance. One thing that could be worth trying, is attaching your 5V supply to Vref directly to bypass the LDO. With a 5V VDD, the Vref voltage will be slightly below 5V. 

    Thanks,

    Alex M.

  • 0 in reply to Alexander Mazany
    Prodigy 60 points

    Thanks Alex!

    It's very helpful to know that the rise and fall times of the UCC27611 should not be impacted by a higher VDD since the driver stage is powered by Vref. I don't have a waveform to post at the moment, but can provide one tomorrow. I've been using a ground spring attachment instead of the standard banana clip to reduce inductance of the scope probe as much as possible.

    The ON loop is definitely longer than the OFF loop as you can see in the layout below. I'll try shortening the ON loop by shorting the OUTH and OUTL pins and removing the farther out gate resistor.

    I'll also try shorting Vref and VDD to bypass the LDO. It's interesting you suggest that as EPC (the GaN Fet provider) also did this when using 5V VDD with the UCC27611 for their laser driver evm. I wondered why they did this, but now it makes sense.

    Hopefully these two changes fixes the slower rise times. I'll report back. 

  • 0 in reply to Ben Alsin
    TI__Genius 11810 points

    Hello Ben,

    I think it is worth trying the 5V tied to Vref before re-doing the board. You could also look at options such as a feedthrough capacitor on Vref, or some way to achieve lower inductance. The loop doesn't look that bad; it will basically always be larger than the off loop no matter what. I'm looking forward to the waveform.

    Thanks,

    Alex M.

  • 0 in reply to Alexander Mazany
    Prodigy 60 points

    I shorted VDD and Vref which helped. I now have a clean rise and fall peak to peak in 10ns. 

    I think ultimately the issue I am having with slow rise times is not the fault of the UCC27611 driver, but is related to the choice of GaN Fet I am using. I am unfortunately still seeing slow turn on times (20ns) of the GaN Fet. The turn off times are around 5ns which is great. 

    I had been using the CSD17313Q2 mosfet for my switching needs (up to 25MHz), but needed more that 30V Vds, thus the GaN Fet came into the equation. The GaN Fet I am currently using has more than double gate charge of that of the CSD17313Q2 (5.7nC vs 2.1nC). I'm thinking if I find a GaN Fet with a lower gate charge on par with the CSD17313Q2 (2.1nC or lower), I should be able decrease the rise times and switch up to 25MHz like I was able to do with the CSD17313Q2. Do you think I'm on the right path with my thinking here? 

    Thanks!

  • +1 in reply to Ben Alsin
    TI__Genius 11810 points

    Hello Ben,

    I think it isn't necessarily the gate charge which is causing the issue, but the other charges. These are related though.

    Here are the parasitic capacitances for the two FETs. The GaN FET has a significantly higher Coss over the Vds range.  These FETs are rating their parasitics at different VDS voltages and loads, so it is hard to do a simple comparison. This is what I think may be the issue, but designing for such fast rise/fall times is challenging so there may be something I overlooked.

    Lastly, is that waveform in the second image the VDS of the GaN FET? if so, then turning on the gate will bring VDS low and off will bring Vds high. Here is a simulation with two FETS, only changing the Coss:

    Given I = C * dv/dt, your rise time (dv/dt) will depend on Ids/Coss. The red waveform had about 1pF Coss, while blue has 300pF. Another thing that causes issues here, is that the current is depending on Vds, and therefore decreases with Vds. 

    Thanks,

    Alex M.

  • 0 in reply to Alexander Mazany
    Prodigy 60 points

    Hi Alex,

    Thanks for your help with this. Sorry I wasn't clear on what that second image was. Yes, it is a waveform of Vds of the EPC2204 fet. I am modulating LEDs in a shunt fet configuration with a constant current (3A) power source. When fet is turned on, the LEDs are shunted and Vds is low. When the fet is turned off, the LED's are on and Vds is high. 

    Given what you have pointed out, I'm going to switch to the EPC2214 GaN Fet. The Coss is much closer to that of the CSD17313Q2 and it is the lowest Coss GaN fet EPC makes that meets the rest of my specs, so hopefully it works!