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UCC2897A: Secondary rectifier overshoot waveform

evanus yupiter
Prodigy 160 points
Part Number: UCC2897A


Dear Sir/Mam

I develop UCC2897A as ACF Converter, with the following specifications:
Vin 60Vdc-90Vdc
Vout 12V
IOut 7A
Fsw 200KHz
Np : Ns 15 : 6 (2.5)
Lp 300uH
Llkg 1uH
Lout : 22uH
Secondary rectifier : Schottky diode SDT10A100P5 (1st board) and Mosfet BSZ146N10LS5 (2nd

I have a major technical issue with both board :
1. Vka (or Vds in SyncRect case) waveform, have very big overshoot, even the PCB trace between diode - Secondary coil and Secondary Inductor are very short. You can see at the attached picture, they are very close to each other, and the Vka waveform is in yellow. I use 1.5 damping factor for the snubber)
2. I do simulation using LTSpice , if the primary and secondary coupling is 1, then there is no issue with the Vka waveform, but when i use 0.995 as the coupling factor, the overshoot become very terrible, then i  add RC snubber with damping factor 1 and even 2, the overshoot still visible, it will not disappear completely., the first (in case oh schottky diode) and up to third (in case of mosfet sync rect) oscilation still visible.

My question are, in the UCC2897A EVM test report.and other UCC2897A ref design report, even there is no RC Snubber at the secondary rectifier, there is no overshoot with Vka or Vds waveform, how can it be? Why i can't make a clear waveform with my board or even in LTSpice simulation if the leakage inductance is present as in the EVM or TI's Ref design ?




Thank you and best regards

evan

  • 0
    TI__Guru 74115 points

    Hi,

    I assume the test report you mentioned is the user's guide. If so, the waveforms are gate to source not Vds. Your waveforms of gate to source also clean.

    The Vds spikes come from the leakage inductance and self driven SR. You cannot eliminate them. But you can play with the RDEL to minimize them. Or adding snubber or clamping to adapt your selected MOSFETs voltage ratings.

  • 0 in reply to Hong Huang
    Prodigy 160 points

    Hi Huang

    Yes, the test report is from EVM user guide SLUU357, and once again you are correct, it's Vgs, but from the schematic, the gate signal is directly come from the opposite SyncRect FET Vds, only 2R2 resistor present. between them. With such low R, I assume both SyncRect VDS should be very clean, if both Vgs as in the test report are clean. 

    Adding snubber actually will reduce the overshoot, but i find different result by adding RC snubber in ACF Sync Rect FET and the Primary NMOS and PMOS.

    In the primary, the overshoot can disappear if i add RC snubber with damping factor 1 and set the RC snubber frequency as same as the ringing frequency, but in Secondary SynRect FET case, even i use 1.5 or 2 damping factor, and i decrease the RC snubber frequency to be 0.5 of the ringing frequency ( in order to let more signal to be absorbed by the resistor), the overshoot still exist. Why can it be like it?

  • 0 in reply to evanus yupiter
    TI__Guru 74115 points

    Hi, 

    If you look at the Vgs carefully you should be able to find Vgs has a gate resistor which can help filter out the spikes.

    Primary side is with active clamp technique which provides certain soft switching. Secondary side is hard switching so it’s switching spikes need stronger effect to reduce.