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Original question:

LM51551: Design challenge

LM51551: LM51551 Vgs spike

Sway Chen
Prodigy 165 points
Part Number: LM51551

Hi Ti experts,

Here is a driver problem that needs your help. Our team designs a 24V to 24V isolation flyback in load 2A. There is a significant spike on Vgs when it is already turned off.

I am trying to use the snubber, cap, and zener to clamp the spike voltage, but it doesn't work. If TI experts can support me with some tips, I will appreciate it.

Parameters:

Vin: 21.6~26.4

Vo:24V 

Load:2A

fs=266kHz

As below you can see,  the Vgs is already down to zero and then turn to 2.56V.  I am not sure if it has been through Vgth.

  • 0
    TI__Guru 65170 points

    Hello Sway Chen,

    Does the ringing change when you are not measuring the Vds at the same time?

    Are you measuring Vgs or the voltage from gate to GND? You need to measure the Vgs differentially without including the sense resistor.

    Possibly you might check if it changes with a transistor with reduced Miller capacitance.

    Best regards,
    Brigitte

  • 0 in reply to Brigitte
    Prodigy 165 points

    Are you measuring Vgs or the voltage from the gate to GND? 

    ->gate to GND, but I changed it to measure the Vgs. The same spike phenomenon I get.

    -> The voltage is up to 2.54V, I am concerned that it may trigger the most to turn on.

    and this one is just mos Vds no sense res

    In addition, I will be very happy if you could give me some advice to solve the first spike Vds.

    I am looking forward to your reply :)

    SWAY

  • 0 in reply to Sway Chen
    TI__Guru 65170 points

    Hello Sway,

    Can you please just measure VGS alone? How do you connect the GND side of the probe? Are you using the pigtail method, see here: https://e2e.ti.com/blogs_/b/powerhouse/posts/how-you-measure-your-ripple-can-make-you-or-break-you

    The diode on the gate is populated in your circuit, right?

    Please check if the spike is reduced when using a FET with lower Gate-Drain capacitance.

    Best regards,
    Brigitte

  • 0 in reply to Brigitte
    Prodigy 165 points

    Hi Brigitte,

    Thanks for your kind support.

    Please check if the spike is reduced when using a FET with lower Gate-Drain capacitance.

    -> The FET is BSC109N10NS3 G and the crss is 14pf. Is it any suggestion about the value? Or do I need to search for a lower-value one?

    The diode on the gate is populated in your circuit, right?

    -> Yes

     How do you connect the GND side of the probe?

    -> I use this type as below.

  • +1 in reply to Sway Chen
    TI__Guru 65170 points

    Hello Sway,

    I would try to check with a FET with lower capacitance to see if this can help. Or you could use a FET with a higher threshold voltage. BTW, I think you could do the opposite test as well, by adding a small external cap between gate and drain and see if the spike increases. But this test might not work out properly.

    On the other hand, when checking out MOSFET datasheet, the threshold voltage is given with 45uA of current. The typical characteristics show a Miller Plateau above 4V and the current seems to be limited below 3V according the transfer characteristics.

    Best regards,
    Brigitte

  • 0 in reply to Brigitte
    Prodigy 165 points

    Thanks, Brigitte for helping me out with this problem, I appreciate it.