BQ76952: After REG0 enable, the levels of the two pins DDSG and DCHG has been pulled up.

Nan Zhang

Part Number: BQ76952
Other Parts Discussed in Thread: TIDA-010216

Hi team,

The levels of the two pins DDSG and DCHG of the BQ76952 are measured to be pulled high immediately after REG0 is enabled. Could you please help to confirm whether the default level of these two pins can be configured as low level? I find the diagram shows that the REG18 pull up the pin instead of REG0. Could you help me to understand it ?

YOURS

NAN

over 2 years ago

0 Jose Couso over 2 years ago

TI__Mastermind 27321 points

Hello NAN,

The DDSG and DCHG pins can be set to follow REG18 or REG1 as described below. REG18 will always be set to 1.8V, whereas REG1 needs the pre-regulators to be enabled.
If you wish that the digital CHG/DSG pins follow the REG1 voltage, you can enable OTP[3] in the DCHG and DDSG config registers.

Please explain the use you intend to give to these pins and also share your configurations.

Regards,
Jose Couso

0 Nan Zhang over 2 years ago in reply to Jose Couso

TI__Intellectual 1895 points

Hi Jose,

Thanks for your reply.

Actually the customer use DDSG and DCSG connecting with mos to control the discharging. They test that after enabling the the REG0, the DDSG and DCSG are pulled up at 3.3V which would make the mos connecting and starting discharging. So they want to know how set the DDSG and DCSG low after enabling the REG0.

I will get the configurations from customer.

YOURS

NAN

+1 Jose Couso over 2 years ago in reply to Nan Zhang

TI__Mastermind 27321 points

Hello Nan,

Nan Zhang said:
Actually the customer use DDSG and DCSG connecting with mos to control the discharging.

For this customer needs to set the [PIN_FXN1 : PIN_FXN0] bits to 10. This will ensure that DDSG pin will act as DDSG. If the lowest two bits are set to 01, it will act as general purpose output and it will not follow the FETs logic.

Nan Zhang said:
So they want to know how set the DDSG and DCSG low after enabling the REG0.

For this to work, the OTP5 bit needs to be zero (DDSG/DCHG is high when DSG is disabled)

For a quick test on the DDSG pin, please tell customer to try setting DDSG Pin Config register as 0x22.

Regards,
Jose Couso

0 Jose Couso over 2 years ago

TI__Mastermind 27321 points

Hello NAN,

Do they have the CHG FET Protections A and DSG FET Protections A registers set to the below description? The device will take up to 250 ms if they do not do this.

Regards,
Jose Couso

0 Nan Zhang over 2 years ago in reply to Jose Couso

TI__Intellectual 1895 points

Hi Jose,

Thanks for your reply. According to you suggestions, I checked with customer. They set the registers correctly. The registers they set are shown below.

Could you please help me to check the registers?

YOURS

NAN

0 Jose Couso over 2 years ago in reply to Nan Zhang

TI__Mastermind 27321 points

Hello Nan,

I see they are setting both CHG FET Protections A and DSG FET Protections A to 0x80. This is not correct. Only DSG FET Protections A should be set to 0x80. The CHG FET Protections A can be set to either 0x98 or 0x18.

On another point, I only see REG0 Config enabled. The pre-regulators are off by default, REG12 Config should also be configured. Maybe this is configured but is not shown in the picture.

Regards,
Jose Couso

0 Nan Zhang over 2 years ago in reply to Jose Couso

TI__Intellectual 1895 points

Hi Jose,

The customer has set the registers as you suggested. But there is still delay on DSG to follow the DDSG. Do you need other information measured by customer? Because of the jet lag, I want to prepare well to accelerate this issue.

YOURS

NAN