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TPS61378-Q1: SW pin under shoot issue

Part Number: TPS61378-Q1


Dear TI expert,

We tested the TPS61378 in our project. Please help check SW voltage overshoot and undershoot issue as below. 

Defines -0.3v in datasheet, but it is -2v in test waveform. Whether can it be accepted? What's the judgment criteria? Thanks.

Best Regards

Bruce

  • Hi Bruce,

    When testing stress on SW, please use non-isolated probe alone and use ground ring like that in the picture.

    And please remove any other probes from the scope.

    Usually the negative voltage is caused by bad layout, but it will not necessarily lead to device damage.

    Best Regards

    Fergus

  • Hi Fergus,

    Yes, the result is tested with ground ring.

    If have clearly value definition, to clarify this result does not have risk. or any explanation to guarantee the result is ok. After all, current result is over datasheet range. Thanks.

    Best Regards

    Bruce

  • Hi Bruce,

    The voltage in the table is DC voltage. For the spike voltage, it is needed to calculate its energy and usually it will not cause damage.

    Best Regards

    Fergus

  • Hi Fergus,

    Thanks for your reply.

    According to your reply, need to calculate its energy, how much energy will damage the IC? whether is our test result waveforms accept? Confirm that it has no risk? 

    Best Regards

    Bruce

  • Hi Bruce,

    it is hard to calculate the energy and also hard to estimate if the energy will cause damage.

    As for your test waveform, it is acceptable, but the result is not confirmed at all conditions.

    But it is recommended to run triple-temp test and aging test to ensure safety.

    Best Regards

    Fergus

  • Hi Fergus,

    According to your reply, it is acceptable. What's your judgement standard or method? Please explain it in detail, then we can check the status with other input voltage or temp...

    It has been taken too much time, please resolve our question in root. Thanks.

  • Hi Bruce,

    The judgement is referred to our full validation test result.

    In the test, the negative voltage also reaches -2V at worst case.

    After all, the stress is related to PCB layout parasitic parameters, temperature and so on, so full condition test is needed.

    Sorry for wasting the time.

    Regards,

    Fergus