TPS22953-Q1: Timing specs at maximum load

Hi Matisse, 

There is a tBLANK time, typically 100 µs, between the SNS voltage exceeding VIH,SNS and PG being asserted high. Since this device's PG is dependent on EN exceeding VIH,EN and the voltage on SNS exceeding VIH,SNS, the delay from EN to PG would not be td+tr+100us unless the VSNS>VIH,SNS level corresponded to the output being at 90%. Instead the total delay from EN at 50% to PG assertion would be td+(time from output at 10% to VSNS>VIH,SNS)+100us. 

Additionally, on the falling side, there is a tDEGLITCH time, typically 5 µs, between the EN voltage or SNS voltage going below their respective VIL levels and PG being pulled low. 

We do not have the tdelay and trise data for Vout=1V, Iout=5A without CT on hand. 

I would recommend using an EVM available here: https://www.ti.com/tool/TPS22953EVM to determine what tdelay and trise you should expect. 

If that is not possible, this would require testing in lab from our side for a typical value. Do note, this value would not be guaranteed by TI as it is not in the datasheet. This value should serve as a design reference only; is this something you would want to move forward doing? 

Best Regards, 

Elizabeth