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LM63625-Q1: question about the reset pin function regrading system power consumption

Iris Shen
Expert 4002 points
Part Number: LM63625-Q1

Hi team,

Three questions:

I see this description in datasheet and don't understand" When EN is pulled low, the flag output is also forced low. With EN low, RESET remains valid as long as the input voltage is >=1.2V(typical)". Does this mean RESET is always low during EN is low? What does "reset remains valid" means?

Customer current configuration is connecting RESET pin to 3.3V with 47k pull up resistor. How to reduce the current consumption of the RESET pin?

Do you have any suggestion for customer to reduce the shutdown quiescent current?

Thanks!

  • +1
    TI__Mastermind 35170 points
    Iris Shen said:
    Does this mean RESET is always low during EN is low?

    Yes, if VIN is greater than  VRESET_V ALID (see EC table for this specification).

    Iris Shen said:
    What does "reset remains valid" means?

    RESET state is deterministic. That is, it is either a true logic 1 (pulled up) or a true logic 0 (pulled down via internal FET).

    Iris Shen said:
    Do you have any suggestion for customer to reduce the shutdown quiescent current?

    If EN is low, but the voltage on VIN exceeds the UVLO of VCC then VCC will be active. In that case, you will be sinking current. A work around could be using VOUT as the pull up source, as VOUT will be deactivated when EN is low.