TPS65219: EN toggling before off-sequence complete

Hi,

Thank You for using E2E. The ON-request on the enable pin is ignored until the PMIC completes the power-down sequence. 

Thanks,

Brenda

Hi,

Here are the responses to the questions in the previous message:

Hirotsugu Kobayashi said:

When does the PMIC complete the power-down sequence?

It depends on the NVM settings. The power-down sequence is gated by the slot duration and the rails being discharged below the SCG threshold. This means the power down sequence will complete after the duration for the last slot finishes and all the rails are below the SCG threshold. The technical reference manual (TRM) for each orderable shows the power-up and power-down sequence along with the duration. If you are using the TPS6521901 specifically, here is the link to the TRM: TPS6521901 Technical Reference Manual (See figure 2-1, 2-2)

Hirotsugu Kobayashi said:

If EN remains high, will it automatically enter the power-up sequence after completing the power-down sequence?

Do I have to turn off VSYS to reboot the PMIC?

If the enable pin goes from low to high while the PMIC is executing the power-down sequence, the device will automatically execute the power-up sequence again after the power-down is complete. Please refer to the TPS65219 online datasheet for a description of the COLD reset, I2C OFF request and Enable pin. These triggers can execute a power-down sequence but only COLD reset doesn't require a new ON-request. 

Thanks,

Brenda

Hi,

The TRM only shows the NVM configurable register settings which are unique for each orderable. All the remaining parameters can be found in the datasheet. The OFF deglitch for the EN/PB/VSENSE pin (when configured as Enable) is shown in the capture below. 

Thanks,

Brenda