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TPS92520-Q1: When the two outputs of the TPS92520 are used in parallel, how much should the time difference between the two UDIMs be controlled?

Jeff Yun
Expert 4155 points
Part Number: TPS92520-Q1
Other Parts Discussed in Thread: TPS92519-Q1,

Hi, team

Hope you are doing well!

My customer parallels the two output channels to support higher current, and they refer to our application report: Paralleling LED Driver Channels to Support Higher
Currents Using TPS92520-Q1 or TPS92519-Q1

For the time difference between two UDIMs, this report requests to control "with very small delay"

Customer what to know how long should this delay be controlled to? Could you please help provide a precise value? 

Thanks & Best Regards

Jeff

  • 0
    TI__Mastermind 23156 points

    All the UDIMS need to be tied together.  Why do you want to separate the signals?  

  • 0 in reply to fhoude
    TI__Expert 4155 points

    Hi, Francis

    Customer wants to do compatible design. When the current demand is small, the two channels are output separately. When the current demand is large, the two channels are output in parallel.

    Therefore, customer doesn't want to connect two UDIMS together. And they want to control the time difference between the two UDIMS within a small range to meet the conditions for parallel output.

    So customer wants to know what conditions need to be met for this time difference?

    Thanks & Best Regards

    Jeff

  • 0 in reply to Jeff Yun
    TI__Mastermind 23156 points

    Do they want to use the TPS92520 or TPS92519?  If they plan to use the 520 are they planning to use register setting to control PWM dimming or use UDIM inputs?  If using registers to control PWM then it will be easy to implement because they can gate both channels enables using one register write of SYSCFG1 register.  Do they have a specific PWM frequency they want to use?  We have a range between 108 Hz to 1507 Hz in our register settings.  To me this is the easiest implementations, but I don't know all of they application requirements.

    -fhoude 

  • 0 in reply to fhoude
    TI__Expert 4155 points

    Hi, Francis

    I have discussed this topic with customer.

    This is a project under development, customer has selected twoTPS92520-Q1s and can't change the hardware design.

    They plan to connect 2 or 3 channel outputs in parallel according to different applications. In 3-channel output applications, the SPI configuration cannot be used for paralleling. 

    Therefore, they want to know what conditions the time difference needs to meet when controlling UDIMs of different channels?

    Thanks & Best Regards

    Jeff

  • +1 in reply to Jeff Yun
    TI__Mastermind 23156 points

    It would have to be sub 1us, or else you run the risk of having one channel causing the current limiting on the other channel, as outlined in the app note.