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TPS7A25: Want to confirm the somewhat odd turn on behavior we experience

Southern Engineering
Intellectual 715 points
Part Number: TPS7A25

Hi,

We step up the input voltage to VIN of the TPS7A2518DRVR in 25 mV steps, with the EN directly connected to VIN. We then experience that the VOUT voltage starts to rise (from 0V) as VIN reaches ~1.3V. That in itself would not be surprising since VIN is then with margin higher than the 0.9V that is stated as the minimum enable voltage. However, as we continue to step the voltage and pass 1.375V, VOUT goes to 0V again. It then stays there until VIN reases closer to 2.1V. 

The load is in single mA range. 

Is this expected behavior, or should we keep looking in our system for some other factor generating this behavior?



  • 0
    TI__Expert 6570 points

    Hello, 

    The Vdo for this device is 210mV, and the minimum Vin is 2.4V. The LDO will not regulate a 1.8V Vout unless Vin is above the minimum value or is greater than Vdo + Vout. 

    The steps are the result of the device staring up in dropout. Vout follows the internal Vref once Ven reaches its minimum turn on voltage (0.9V). Because Vin is too low for Vout to regulate at its expected voltage, Vout ramp is stopped, creating steps. The LDO turns off after about 30 seconds because Vin is lower than than Vdo + Vout.  

    You can fix this by enabling the device after Vin reaches 2.4V or ramping Vin quickly, based on the scope shot it looks like it takes a full minute for the device to turn on. Here is an app note that explains startup overshoot a bit more in depth. 

    I hope this is helpful, please let me know if you have additional questions.

    Best regards,

    Erin

  • 0 in reply to Erin Thibeault
    Intellectual 715 points

    Thank you Erin, that was great input.

    Hope you do not mind that I have a few follow-up questions. I had a first set of questions written down here, but after some further analysis I decided to focus on these details (so I adjusted a bit):

    1. I believe I should be able to avoid the early start-up of the LDO described in the initial question, by applying a 1/3 voltage divider between VIN and EN. However, I would need to know that a) I always manage to turn on the LDO with my VIN level and 2) that I do not turn it on too early. The datasheet only seem to state the min 0.9V level, but no max. Would you have any input to that, or how would I know if my VIN level will be high enough to trigger EN?

    2. A VIN around 2.15V seems to be the level where the LDO finally starts up and can supply 1.8V in my setup. However, I see oscillations due to VIN dropping as soon as the LDO starts supplying charge to the output capacitors (see picture below). I guess this is related to that the MOSFET is essentially fully open when starting from a low voltage, while the output capacitors are discharged, plus that I have 240 ohm in series right behind the 1 uF + 100 nF input capacitors. The 240 ohms are a requirement, they cannot be removed or reduced.

    I ran a test with the LDO PSPICE model to get a feeling for how far away from working I seem to be. The result was that if I reduced the output capacitance to 1 uF (the minimum according to datasheet, here set to 500 nF considering DC derating at ~1.8V) I still needed around 15 uF (derated value) on the input to get rid of the oscillations. That should correspond to about 47 uF at the start-up voltage (2.5-3V).

    Any comments or suggestions on how to solve this oscillating behavior now that I cannot remove the 240 ohm in series? 

  • +1 in reply to Southern Engineering
    TI__Expert 6570 points

    Hello,

    No problem at all, I'm happy to support! 

    1. The maximum recommended enable voltage is 18V. You can tie enable directly to Vin, once Vin is greater than 0.9V the device will be enabled. If Vin is ramping slowly, it may be best to power enable separately. Based on your first scope shot, it looks like the device is enabled for ~60 seconds before the Vin has reached the minimum voltage it needs to regulate Vout, putting the device in dropout. 

    2. Vout (1.8V) = Vin (2.15V) + Vdo. Maximum dropout voltage per the datasheet is 340mV, so you you are operating very close to, or just barely in dropout. Vdo is not a set value, and increases with current. The higher current you're driving, the greater dropout voltage your LDO needs to regulate. 

    Starting the LDO in dropout is the cause of these oscillations. Vout cannot track internal Vref in dropout, and follows Vin. The error amplifier drives the gate voltage of the pass FET to the rail, and the FET is fully on. When output reaches the regulation point (in this case, about it looks like 300mV less than Vin) the error amplifier has to transition the gate voltage away from the rail. the time it takes for the error amplifier to respond causes overshoot, as the output is still following the input. 

    If its not possible to enable until Vin is greater than Vdo + Vout to allow for proper regulation, a quicker Vin startup could reduce oscillations. Adding a larger input capacitor, and decreasing your output capacitor could also help reduce ripple. 

    I hope this is helpful, please let me know if you have additional questions. 

    Best regards,

    Erin

  • 0 in reply to Erin Thibeault
    Intellectual 715 points

    Thank you for a thorough answer!

    Unfortunately I think I was a bit unclear in question #1 (about the EN max limit). I meant the max high level for triggering EN. The datasheet states a minimum of 0.9V, but I was afraid that if I design for that with too little margin I might not enable some samples. For instance, if I need to have the LDO turned on when VIN = 2.5V, I could design a 2.5k + 1k voltage divider from VIN to EN that produces 1V at EN with VIN = 2.5V (where 1V is 0.9V + 100 mV margin). However, if the max high level voltage for the EN pin is 1.1V, then some samples would not turn on, or turn on first if I apply an even higher VIN. 

    Would you have any comment to what the maximum high level EN voltage might be, to ensure turning on all samples?

  • 0 in reply to Southern Engineering
    TI__Expert 6570 points

    Hi, 

    I think I understand what you mean. Enable is triggered if the voltage on enable is greater than 0.9V and less than 18V. Maximum enable voltage is equal to the maximum input voltage, so that enable and VIn can be tied without damaging the device.

    Does this answer your question?

    Best regards,

    Erin