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TPS75933 - Unable to turn off memory device using the enable/shutdown function

Hi,

I've been experimenting with the enable/shutdown function of the TPS75933KC 3.3V fixed output LDO to inhibit the power of an EEPROM; however, I'm noticing some unusual and undesirable behaviours. The circuit, which is part of a multi-voltage supply system (i.e. 3.3V_processor and 3.3V_eeprom), consists of an LDO and its Vout (3.3V_eeprom) is connected to the Vcc of the EEPROM. The common data/address bus of the EEPROM is driven by a processor operating from a separate power source (3.3V_processor) that is never turned off.

The problem is that when the LDO is in shutdown mode (enable pin pulled up), 2.7~3.3V could still be detected on the Vcc pin. After performing a few isolated tests, I have concluded the following: 

1) If the data bus of the EEPROM is driven by the processor while the LDO is in shutdown, a voltage could be measured on the Vcc terminal of the EEPROM. 2) The current flowing back to the LDO (i.e. from processor data bus -> eeprom data bus -> eeprom Vcc terminal -> LDO output) is only limited by the internal resistance of the LDO. If I take out the LDO and tie the Vcc of the EEPROM to ground, the 3.3V_processor voltage supply goes into over-current protection. 

Could someone please explain these observations and suggest a way to properly turn off the EEPROM using this particular LDO. 

  • I think your measurements are very clear in this case.  The voltage is not coming from the LDO but is backfed through the EEPROM's data bus voltage.  The LDO is not responsible for this.

    Why is this a problem?  You need to pull the data lines low in order to not backfeed a voltage onto Vcc.

  •  

    What if pulling the data lines low is not a viable option as the bus is also shared by other memory devices. I'm afraid that the 2.7V on the Vcc is enough to enable the internal circuitry of the EEPROM. The original idea was to power off the module completely so that it is immune to radiation effects. Is back-feed quite common with memory IC's? If so, what are some design techniques that could be utilized to overcome it? Could you recommend other power switching/inhibiting TI products that are suitable for my design.

     

     

  • Yes, this is a common issue with processors and memory that have many different voltage rails and data lines connecting many devices.

    Changing ICs won't help you.  The problem is in your EEPROM.  It is what is passing the voltage on its data lines to its input.  You should contact them to see what they recommend.

    All I can recommend is that you disable the EEPROM with its enable pin.  If it doesn't have one, then you need to contact whoever makes it.

  • Hi Martin,

    I think that many devices have this "back-feed" problem that causes voltages to appear on various input lines un-expectedly.  We typically recommend that customers use a diode in series with the Vcc line (3.3V_eeprom) from the LDO - but of course this doesn't stop the problem but effectively blocks current flow (this assumes that I am understanding your problem correctly).

    As far as recommending an alternative LDO, you can send your specifications and we will do our best.

    Bill

  • Thank you Chris, thank you Bill. I think I have enough to go on. I'll contact the manufacturer to see what they recommend.