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UCC28951: What is the evaluation board UCC27714EVM-551?

r.uchida
Prodigy 90 points
Part Number: UCC28951
Other Parts Discussed in Thread: UCC28950

Hello,

I am thinking of buying an evaluation board to better understand ucc28951.

What is the most effective way to use it?

Is there anything else I need to prepare for effective use?

  • 0
    TI__Guru 50190 points

    Hi,

    Any of our EVM's work best as a real-time simulator. They are best used to understand how the device(s) are working when everything is perfect. This can be used as a baseline for your own design if you try to design for a different output voltage or power level. The EVM guide is the best way to prepare for how to use the EVM.

    I hope this helps. 

  • 0 in reply to JCHK
    Prodigy 90 points

    Hello,

    Why are the CS and VREF pins of ucc28950 connected?

    In the application note slua560d, the CS and VREF pins were separate.

    Also, why are the values of the resistors connected to ADELEF and ADEL, which are necessary to set the delay time of FET, not set?

  • 0 in reply to r.uchida
    TI__Guru 50190 points

    CS is pulled up to VREF typically via a 1k resistor. This is the output of a current sense transformer:

    ADEL and ADELEF are used to optimize the efficiency of the design by adjusting the dead time. I would have to check with the designer of the EVM to see why this wasn't necessary to set.

  • 0 in reply to JCHK
    TI__Guru* 86286 points

    Hello,

    The CS pins in the EVM design is not connected to VREF.  A resistor divider from the reference is connected to ADEL and ADELF to use a fixed delay approach as described in application note slua560d.

    The fixed delay approach is the most popular design using the PSFB.  It is easy to setup and is quite efficient with ZVS.  The adaptive delay approach is used by some to reduce body diode conduction on the primary of the H Bridge.  This efficiency improvement from removing the body diode conduction is marginal compared to what you achieved for ZVS.  To setup the timing is also a lot of trial an error.  For these reasons most designer choose the fixed delay approach described in application note slua560d.

    The adaptive delay technique which would would have resistor dividers from CS to ADEL and ADELEF.  If you decide to use this technique I believe there is information in the data sheet on how to use adaptive delay. Also you would just have to unpopulated the resistors between ADELF and ADEL to VREF.  Then you would populate the resistors between CS and ADEL AND ADELEF.

     

    Regards,

    .     

  • 0 in reply to Mike O'
    Prodigy 90 points

    Hello,

    I was able to understand that there is a difference in the way resistors are connected in fixed delay and adaptive delay systems.

    Why doesn't the EVM design set ADEL and ADELEF?

  • 0 in reply to r.uchida
    TI__Guru* 86286 points

    Hello,

    It is because the EVM uses a fixed delay approach. 

    Some engineers like the ability to try adaptive delay.  The EVM can be modified by changing the resistor connections so adaptive delay can tried.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 90 points

    Hello,

    In the application note slua560d, I believe that to set the delay range, the voltage of VREF is divided by a resistor to set ADEL and ADELEF.

    What is the reason why this was not the case for EVM with the same fixed delay method?

    Are you saying that you want to use both the fixed delay approach and the adaptive delay approach, so you have not set them up?

    Then, if I design with a fixed delay approach, does that mean I should just set it up like the application note?

  • 0 in reply to r.uchida
    TI__Guru* 86286 points

    Hello,

    You inquiry is under review.

    Regards,

  • 0 in reply to Mike O'
    TI__Guru* 86286 points

    Hello,

    Let me study the EVM and get back to you.  It sounds like something is different compared to the application note.

    Regards,

  • +1 in reply to Mike O'
    TI__Guru* 86286 points

    Hello,

    I looked at the EVM and it looks like the designer tied ADEL and ADELEF to ground through a 0 ohm resistor.  Setting the voltage at these pins to zero is an option.

    In the equations TABSET, TCDSET and TEFSET you just need to set CS to 0 V in the equations to calculate the delays.  To select the timing resistors you just need to algebraically solve for RAB, RCD, and REF.

    The other option you have is to set the delay timing by setting the ADEL and ADELEF with a voltage with resistor dividers from Vref to these pins as described in application note slua560d.

    The UCC28951 is a very versatile controller.  You can design it for fixed delay or adaptive delay.  You can adjust the voltages at ADEL and ADELEF with a voltage divider off of Vref, or the CS to get different timing behaviors. As you discovered you, can short the ADEL and ADELEF pins to ground if the designer choose.

     

    Regards,

  • 0 in reply to Mike O'
    Prodigy 90 points

    Hello,

    Why is the PWRGND wire drawn under U4 on the evm board?

    Is electrical insulation involved?

  • 0 in reply to r.uchida
    TI__Guru* 86286 points

    Hello,

    Do you have a picture of what you are mentioning?  Could you share it?

    Regards,

  • 0 in reply to Mike O'
    Prodigy 90 points

    Hello,

    I mention about the ditch circled in red.

    Also, this is a different question, but is it possible to use EVM with low input voltage?

    Or do we always need 370~410V input voltage?

  • 0 in reply to r.uchida
    TI__Guru* 86286 points

    Hello,

    I am reviewing your inquiry and will get back to you shortly.

    Regards,

  • 0 in reply to Mike O'
    TI__Guru* 86286 points

    Hello,

    That cutout under the digital isolator separates the primary from the secondary.  It was done to meet creepage and clearance requirements.

    In regards to the input voltage the transformer was designed for a 370 V input.  So you will run into duty cycle and load regulation issues if you go below the minimum input range of the EVM.

    If you need to design for a lower input range the transformer in the EVM will not work. You would need a new transformer with a different turns ratio and magnetizing inductances.  Application note slua560d has a section on how to calculate these values ;as well as, RMS currents.  You can then use these values to have a new transformer designed for you application.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 90 points

    Hello,

    In the user's guide, there is a diagram showing the measurement of FET waveforms, but how are they measured?

    Is there a place where an oscilloscope probe can be connected?

    Also, what is LOOP- of TP2 and LOOP+ of TP3 for?

  • 0 in reply to r.uchida
    TI__Guru* 86286 points

    Hello,

    I am reviewing your inquiry and will get back to you shortly.

    Regards,

  • 0 in reply to Mike O'
    TI__Guru* 86286 points

    Hello,

    Are there any specific figures you are discussing, could you reference them?

    When it comes to taking test waveforms from FETs.  I have done the following.

    1. With through whole FETs you may have access to the gate, drain and source which you can probe directly without any additional circuitry.

    2. In some designs I have done, I have added test points for testing the FETs.  If they are present they will be shown in the designs schematic.

    3. If test points are not available and I don't have easy access, I have solder test points on my design to evaluate FET peformance.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 90 points

    Hello,

    Regarding the U4 isolator, the part number in the schematic and the part number in List of Materials in the user guide are different, which is correct?

  • 0 in reply to r.uchida
    TI__Guru* 86286 points

    Hello,

    I am reviewing your inquiry and will get back to you shortly.

    Regards,

  • 0 in reply to Mike O'
    TI__Guru* 86286 points

    Hello,

    More than likely when the board was designed one opto was used.  Do to the part shortages the opto was swapped out.  So both opto isolators should work in the desing.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 90 points

    Hello,

    There are D3,5,7,8 Schottky diodes between the gate and source of each of Q1~Q4, what role do they play?

  • 0 in reply to r.uchida
    TI__Guru* 86286 points

    Hello,

    I am looking into your inquiry and will get back to you shortly.

    Regards,

  • 0 in reply to Mike O'
    TI__Guru* 86286 points

    Hello,

    They protect the DRIVE pins of the UCC287714 from negative voltages in regards to the FET source pins they are driving.

    In some cases the parasitic inductance in traces can ring with parasitic capacitances.  To protect the driver pin a shottky diode is added from the drive pin to the source pin of the FET at the gate driver integrated circuit. 

    Regards,