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LM5116: Question regarding separating PGND and AGND

Anthony Marini
Prodigy 50 points
Part Number: LM5116

I have a customer who would like to use one of our eGaN HEMTs as the external switching elements for the LM5116 IC controller.

The circuit that I would recommend to them looks like the following (shown just for the power train elements):

The transistors Q1 and Q2 are the EPC Space FBG10N05A. This is a 100V/5A eGaN HEMT, and its data sheet may be found here: https://epc.space/documents/datasheets/FBG10N05A-datasheet.pdf. The transistor package has four pins, gate/drain/source along with a "source sense" pin. The source sense pin is at the same potential as the source connection directly on the transistor's die. The source sense pin is a "clean" connection to the transistor's source connection at the die, bypassing common source inductance (CSI)and resistance (CSR). This allows the gate drive loop current to be decoupled from the drain-source current, and the result is a gate drive signal that is very clean, without perturbations caused by the high-frequency drain current due to CSI and CSR.

To get the maximum benefit from the source sense pin (SS) it is necessary to connect the return of the gate driver to that pin. For the high-side driver and transistor (Q1), this is possible because the SW pin on the LM5116 IC is the return for the high side gate driver (output at HO). The low-side situation is complicated because the low-side gate driver (output a LO) return is common with the PGND pin on the IC. In order to achieve the proper gte drive loop situation, the PGND pin must be connected to the SS on the low-side transistor, Q2. However, in the LM5116 data sheet there is the recommendation to "Connect to PGND and AGND through the exposed pad ground connection under the LM5116". This means that the situation in the example circuit, above is not possible because the voltage at the PGND pin would be at worst-case peak over 139mV:

With a peak voltage across RS determined by the inductor ramp and the response time from the current sense comparator to the gate driver output.

My question is can the PGND and AGND pins be at different potentials, or are these nodes at the same potential on the die, and MUST be connected together on the application PCB??? As you can see, the maximum voltage offset between PGND and AGND (the actual system "ground" return) would be 150mV, maximum. If AGND and PGND are indeed separate nodes on the die, can these two return signals have the differential potential of less than 150mV between them, with the PGND pin being at the higher potential?

Any help that you can provide me, or insights regarding the LM5116 would be greatly appreciated.

Best regards...

Tony Marini
Power Technologist
EPC Space, LLC
www.epc.space

  • 0
    TI__Guru 59291 points

    Hello Anthony 

    The max VCC of the device is 7.7V while the abs max of Vgs of FBG10N05A is 6V. You cannot use LM5116 in your application. 

    This means that the situation in the example circuit, above is not possible because the voltage at the PGND pin would be at worst-case peak over 139mV ==> PGND should be electrically connected to the AGND, DAP, and CSG pins. 

    As you can see, the maximum voltage offset between PGND and AGND (the actual system "ground" return) would be 150mV ==> AGND and PGND should be tied together. Very high frequency switching noise can make ~ 10-50ns voltage spikes between AGND and PGND. 

    -EL 

  • 0 in reply to EricLee
    TI__Guru 59291 points

    Please let me know if you have any other question.

  • 0 in reply to EricLee
    Prodigy 50 points

    Hi Eric,

    Please note that there is a 5Vdc external/adjunct power supply connected to the VCCX pin. This will satisfy the 6V absolute maximum gate-source voltage requirement.

    My question is more related to the grounds, AGND and PGND on the IC. I don't understand the "This is wrong statements!". MY question is are AGND and PGND connected on the LM5116 die and at the same potential?

    It seems from your reply that they are NOT. If they are not, how are the 10-50ns voltage spikes generated? I would think the current flowing out of the AGND pin is due to the low power circuitry that performs the regulation and control functions on the IC. And the current that flows out of the PGND pin is due to the current spikes of the low-side gate driver that drives the gate of the external low-side power switch.

    If AGND and PGND are tied together on the die, then the wirebonds from the die to the package will carry half the total current each and it won't be possible to get the differential voltage spikes you mention. The ONLY way to get voltage spikes between the two is if they are separate.

    What is the magnitude of the voltage spikes that can be expected by grounding the device in the manner that I showed in my diagram?? What gate drive current peak amplitude is assumed? This current can be reduced with a series gate resistance for the low-side HEMT. Even a 5 Ohm resistor would reduce the peak gate current for the low-side driver by more than half than if no resistor is used. And that would certainly reduce the voltage spikes encountered.

    And if the AGND and PGND nodes are indeed separate, there has to be a "well structure" and associated diode present. Since AGND has less current flowing, it will naturally be at the lower potential (closer to 0Vdc) and PGND will "bounce" higher with respect to it because of the high current spikes at the edges of the gate drive signal. It would make sense in this situation that the cathode of this well structure is connected to the AGND pin and the anode to the PGND pin.

    Now, I can see the gate switching event taking on the order of 1-2ns because the Ciss of the FBG10N05 is 233pF, maximum and the gate driver pull-up resistance for the low-side is ~5 Ohms. So I don't understand where the 10-50ns duration voltage spikes you quote come from?

    So I guess my question is are the AGND and PGND internally connected on the LM5116 die? And if they are not, can these pins tolerate a 150mV offset from the AGND (connected to 0Vdc) and the PGND (connected to the positive side of the current sense resistor??

    Sorry for being persistent...but if there's any way the grounding scheme I've previously sketched will work, it will save me having to use a current sense transformer/scaling resistor to replace the current sense resistor. 

    Thanks again.

    Tony

  • 0 in reply to Anthony Marini
    TI__Guru 59291 points

    Hello Anthony 

    • At the beginning of the device starts up, VCC is regulated by the device. It might be better to consider a device which provides logic FET gate drivers. 

    • My question is are AGND and PGND connected on the LM5116 die and at the same potential ==> No, they are connected through some other components on the die (I am not allowed to disclose the detail silicon schematic). But it is recommended to connect AGND and PGND together on PCB. I am not sure the device will be able to work properly in mass production if PGND is not connected to ground.  
    • How are the 10-50ns voltage spikes generated.==> This voltage spike can be generated by the switching operation of the external switches due to the parasitic of the PCB and/or the source to drain forward voltage drop. 10-50ns duration is from MOSFET. eGaN should be better. 

    -EL