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TPS3897: Power On Behaviour

Glenn Wagner
Prodigy 10 points
Part Number: TPS3897

Hello,

We are using the TPS3897P with tpd(r) set to 5sec via capacitance. 

When the device is powering up, we have SENSE coming up ahead of Vcc, then the ENABLE goes high about 200ms after VCC.

Since ENABLE is after SENSE and VCC are already high, we "thought" that the output would go high immediately (tdp = 200ns), but instead, we are seeing SENSE_OUT being held low for the 5sec before rising high.

Is this to be expected on powerup?

Thanks,

-- Glenn

  • 0
    TI__Genius 12985 points

    Hi Glenn, 

    Thank you for your question. Could you please provide a full schematic so we can better assess the situation?

    Thank you again for your question and patience,

    Joshua Austria

  • 0 in reply to Joshua Austria
    Prodigy 10 points

    Hi Joshua,

    I put together a spice simulation to illustrate what we're seeing.

    In the schematic I've used 500nF for CT which equates to approx 2s from SENSE rising to SENSE_OUT rising.

    In all 3 cases, SENSE is HIGH 0.5s before VCC.

    Image1 - Enable in line with VCC

    Image2 - Enable delayed by 1s after VCC

    Image3 - Enable delayed by 2.5s after VCC

  • 0 in reply to Glenn Wagner
    Prodigy 10 points

    I'm also thinking that this is now intended behavior ... we missed a note under the Timing requirements section when we were first evaluating the part:

    2015 datasheet has the following under the table in Section 7.6

    "(1) During power on, VCC must exceed 1.7 V for at least 50 μs (plus propagation delay time, tpd(r)) before output is in the correct state."

    Unfortunately the timing diagrams do not display the power on behavior very well.

  • +1 in reply to Glenn Wagner
    TI__Genius 12985 points

    Hi Glenn,

    It looks like you are correct about it being intended behavior. Thank you for sharing your schematic and screenshots. Please let us know if any other help is needed. 

    Joshua Austria