This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BMS IC selection

Other Parts Discussed in Thread: BQ79616, BQ76PL536
  1. Query: Dear TI team, We want to use external mosfet for balancing along with BQ796xx. could you please suggest us how to connect external mosfet to BQ796xx. Also please comment important points need to be taken care while using external mosfet. Kindly consider this as upmost high priority. Thank you!
  • Hello Shankar,

    Please see the image below for general format of external cell balancing circuitry.  Some additional notes for external balancing are as follows:

    • We recommend using a zener diode instead of a regular diode in the D1 position.
    • Ensure that you place a CB capacitor from the highest CB pin to BAT for hotplug robustness.  This component is often overlooked.
    • Adjust the Rexbal resistor to fit your balancing current needs: Rexbal + (FET Rdson) = Vcell / (desired balancing current in A)
    • Please use care when selecting the external FET.  Be especially mindful of the FET threshold voltage (Vgsth) and drive voltage from gate to source.  If the Vgsth of the FET selected is too high or too low, this can lead to either no FET turn on, or accidental FET turn on, respectively.
    • If the cell balancing capacitor value is too high, this can lead to accidental FET turn on if the FET Vgsth is low.  If the normal 0.47 uF Ccb value is causing issues in simulation, consider switching to a Ccb value of 4.7 nF.

    Best,

    Andria

  • Hi Andria,
    Thank you for this. Yes,
      We have gone through this but there is some issues Or query as below
    1) Can we turn ON all cell balancing at the same time ?
    2) Can we turn ON two - three or more adjacent cells at the same time.
    3) How to calculate Rgate & RBAIS value in above schema.
    4) The other aspect is the Vds voltage stress when every other cell is being balanced.
    As illustrated in below image the top and the bottom cells are being balanced. Due to the cell-balancing bias, the middle internal switch M2 is seeing a higher Vds, which may exceed the maximum Vds it can sustain.
    Could you help us on these queries answer with each point by point?
    Thank you!
  • Hi Shankar,

    Thank you for clarifying what questions you had. In response:

    1) No, you cannot balance all cells at the same time.  A maximum of 8 cells can be balancing at any given time.  Please see section 9.3.3.1.2 in the BQ79616 datasheet for more information.

    2)Yes, you can balance consecutive cells, but only 2, not 3.  For example, simultaneously enabling the FETs for 1, 2, 4, 5, 7, 10, 12, and 14 is valid, but simultaneously enabling the FETs for 1, 2, and 3 is invalid.  Please see section 9.3.3.1.2 in the BQ79616 datasheet for more information.  Please note that this applies to internal FETs, not external FETs.

    3)

    • Rgate is determined by the inrush current you desire at the gate of your FET. 
    • Rbias is determined by how much current you want flowing through the internal FET, and what you want for your Vgsth value. 
      • To maximize Vgsth, make Rbias greater.  To avoid choking current through the internal FET, make the bias resistor smaller.
      • This principle is due to the internal FET Rdson and bias resistors forming a voltage divider circuit.  Essentially: Vgs = Vcell ((Rbias / (2*Rbias + Rdsoninternal)).  If the Rbias resistance is increased, then the effect of the internal FET Rdson is minimized, leading to a higher Vgs votlage.
      • You could start with an Rbias resistance of 1 kOhm, then vary the resistance up or down to meet system needs based on the circuit simulation you create.

    4)  The Vds for the internal MOSFETs will be okay.  Just ensure that you do not exceed the voltage specs listed for the CB pins in the BQ79616 datasheet.

    Best,

    Andria

  • Hi Andria,
    Thank you for this.

    Below question were specially regarding external MOSFETs related . Could you please reconfirm your answer is for the external mosfet ?

    External MOSFET related:

    1) Can we turn ON all (at least 8) external mosfet cell balancing at the same time ?
    For example:
    When the adjacent internal FETs M1 and M2 are turned on, no current is flowing through Rext2 because Ibias through M1 and M2 cancel at
    Rext2; therefore, Q2 remains off even when the internal switch M2 is enabled.


    2) Can we turn ON two - three or more adjacent external mosfet at the same time?
    For example:
    As illustrated in Figure, the top and the bottom cells are being balanced. Due to the cell-balancing bias, the middle
    internal switch M2 is seeing a higher Vds, which may exceed the maximum Vds it can sustain.


    Thank you!
  • Hi Shankar,

    My apologies for confusion before. The BQ79616 does allow for adjacent cell balancing with internal FETs, but you are correct that you should not balance adjacent cells for external cell balancing.  It will cause FET turn on issues.  You can still balance up to 8 cells with external FETs--just not adjacent cells.

    To confirm your questions point by point:

    1) Yes, you can turn on balancing for up to 8 cells with external FETs, but you CANNOT balance adjacent cells with external FETs.

    2) You are correct that cell balancing will cause higher voltages across the internal FETs than would otherwise occur.  This increase in voltage should not exceed 2*Vcell, however, which should be well below the abs max spec in the BQ79616 datasheet.  Is there a particular voltage value you were expecting that was estimated to exceed the datasheet specifications?

    Best,

    Andria

  • Thanks Andria for reconfirmation on these query.

    Could you please suggest any other ICs which supports external MOSFET balancing support with above requirements ( can turn on adjacent cell balancing with external MOSFET min 8 cell at a time).

    FYI: This was the showstopper for releasing our final product schematic and after confirmation now it becomes critical for us. Would be really appreciates if you or TI team can help to suggest or proposal alternate or any other ICs which could support these feature with stackable and/or daisy chain feature.

    Thank you!

  • Hi Shankar,

    Currently, our external balancing FET options all prevent adjacent cell balancing due to the reasons discussed above.  Circumventing these issues may be possible, but it would most likely require more FETs and components and extensive design efforts.  Currently, we do not have documentation or designs that support both external balancing and adjacent FET balancing that I am aware of.

    May I ask what your target balancing current is?  The BQ79718 can support up to 300 mA of balancing current without the use of external FETs, so this may be of interest to you.

    Best,

    Andria

  • Currently, we do not have documentation or designs that support both external balancing and adjacent FET balancing that I am aware of.

    => Hmm, this is really not good news for us. 

    Could you please confirm on this BQ76PL536 ( I think it has 6 cell external balancing) but want reconfirm on adjacent external MOSFET balancing?

    May I ask what your target balancing current is? 

    => Our Target is min 8A-10A and  max 16A to 18A ( yes it is in Amps).

  • Hi Shankar,

    This is very high balancing current.  You would definitely need external FETs.  Unfortunately, I do not think this would be feasible for any of our devices, due to your desire for balancing adjacent external FETs.

    Best,

    Andria