UCC21755-Q1: Gate drive power problem

Hi Erfan,

The UCC21755 has an overcurrent protection pin (DESAT) that measures the voltage across the switch and then will turn off the output if it detects a voltage above a certain threshold. It seems that this circuit is not yet set up correctly. Can you share your gate driver circuit schematic? I can help you to adjust it. You can also use a version of this device with a lower threshold (OC) for a SiC Fet, such as UCC21710.

Best regards,

Sean

Hi Sean,

Thank you so much for replying so quickly.

Sure:

It can be the Desat, but if desat acts and turns off the gate driver, will the gate driver turn on itself automatically? I connected the RST/EN pin to 3.3V.

Cheers,

Erfan

Hi Efran,

If DESAT is triggered the nFLT pin and GATE driver output will latch LOW until the the gate driver is reset by either power cycling or sending a low pulse to RST pin.

Since the gate driver seems to be toggling ON and OFF I don't think the DESAT function is the cause for these waveforms. The output changing states could be due to noise being on the input pins but looking at the waveform it doesn't seem like the input is changing as much the output.

• Are you using the full scope bandwidth to ensure the noise on the input signal is accurately being captured? (Also have to use a tight probing look to make sure not to introduce additional noise to the measurement)

Another thing we could check is the VDD supply. Seems like the pulses ON and OFF are pretty periodic.

• Could this potentially be the bias supply for the gate driver not behaving as expected?
• Could you probe VDD-COM while running this test to see if the voltage remains stable during the turn-on?

Best regards,

Andy Robles

Hi Andy,

We checked input voltage, there is no voltage drop across it but it's noisy. I wondered what the value of the bypass capacitor must be in VDD-COM. Do you think using a big value of capacitors there can cause these glitches and bring the noise into the system? We're using around 15uF, (10uF+4.7uF+0,1uF)

Regards,

Erfan

Hello Erfan,

Sean or Andy is out of the office at the moment. They should respond to you by tomorrow.

Regards,

Hi Erfan,

In the first image, there is a deep spike on the blue input before the output starts to pulse low. Could the problem be with VCC decoupling? Is there another switch in the circuit that is switching at that time? 

I do not know what to make of the second waveform.

Hi Sean,

We actually checked VCC it's 5V, and it has some ringings on it but they're not that big to switch off the gate driver. Also, VDD-VEE is checked, it looks alright too. 

If you could see the attached photo, the blue waveform is (Vgs), the yellow one is (VDG, not VDS), the pink one is (Gate current), and the green one is (Input of the Gate driver). As can be seen, frequently, the gate drivers turn off, and then on. Also, there is a 2nd glitch in the current. Plus, when this phenomenon occurs, there is a drift in the VDG's turn-off time, please second the attached 2nd and 3rd photos.  The desat is de-activated, so is there anything that can push the gate driver to switch to the OUTL path? As the input is not switching off, what else can push the gate driver to switch it to OUTL?

Do you think what is the issue here? Noise? PSU voltage? or a fast dv/dt? or a latching or slew rate?

Kind Regards,

Erfan

Hi Erfan,

Is this for a buck converter? Is there a bootstrap supply to power the high-side driver or is there an isolated supply?

Maybe there is something going on at a wider system level that is affecting the gate driver's operation.

Best regards,

Sean

Hi Sean,

It's for a buck-boost converter. No, there are two isolated supplies for the half-bridge FETs. 

Can the clamp circuit due to the noise wrongly switch on and turn on the OUTL path?

Regards,

Erfan

What is the part number of the SiC FETs that are being driven? Maybe the load is too high to drive them in parallel. Does the problem persist if you only drive one SiC FET?

Hi Sean, it is NVBG020N120SC1. Even with one the problem still exists. I think it must be the layout, so possibly we have to re-do the layout.

Regards,

Erfan

Hi Erfan,

If you provide schematic and layout files we can hold review to make sure the design is following the drivers best practices. If you don't feel comfortable sharing files here we can take the discussion to email.

Best regards,

Andy Robles

Hi Andy,

No problem, I can share those files over the email if you could provide me with an email address please? Also, in which format you want to have the files?

Kind Regards,

Erfan

Hi Erfan,

I just send you an E2E friend request with my email included. You can contact me there and we can continue the conversation. Please add the link to this E2E thread in the email to keep the background of the thread.

For the schematic files PDF or just an image of it would be okay. For the layout if you can share Altium files, PDF of all layers or even just images of all layers.

Best regards,

Andy Robles

Hi Andy,

I couldn't find the email address, so I had to send all of them to you through the private message. I wondered if you received them yet?

Kind Regards,

Erfan