TPS62A02: How to evaluate maximum capacitive load

Hi,

How is the placement done for the output capacitors? Is it placed near to the IC or far from it?

What is the end application? Is your application subjected to variable loads?

Let me know, Thanks!

Best regards

Sneha 

Hi Sneha,

Load will be close from the TPS62A02. Supply will be used in a transmission system over 1G Ethernet.  BW will change on the 1G so it may affect the load.

One TPS62A02 will supply a small FPGA and the other a will supply an 1G Ethernet PHY.  I also plan to have a TPS62A02 to convert 5.5V to 3.3V.  The 3.3V will supply two TPS62A02  to generate 1.1V and 1.2V.

Hi Charles,

Thanks for providing additional details. Would you like to add 500uF output capacitors for all the three rails?

As per the data from our design team, the output capacitance up to 75uF should be fine in terms of stability. However, we have not checked for more than 80uF. 

I would recommend if you would like to add more output capacitors, please perform the loop stability test in your application and verify the gain and phase margin.  Please refer to this app note: https://www.omicron-lab.com/fileadmin/assets/Bode_100/ApplicationNotes/DC_DC_Stability/App_Note_DC_DC_Stability_V3_3.pdf

Thanks!

Best regards

Sneha 

Hi Charles,

Do you have further questions here? If not, please close this thread. 

Thanks!

Best regards

Sneha