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TPS7A45: Minimum output capacitor for stability

Romain Rosset
Prodigy 10 points
Part Number: TPS7A45
Other Parts Discussed in Thread: SN65LVDS2, SN65LVDS1

We are using a cascaded configuration of TPS7A4501 to supply 2x SN65LVDS1 and 2x SN65LVDS2 so around 30mA max.

As we are powering the circuit in sequence and we can't soft start this part, we have stumbled upon a problem because the second LDO is inducing a high spike of current to the recommended 10uF low ESR output capacitor which can induce a glitch in the LDO upstream and trigger our voltage monitoring device into a reset due to the voltage brown-out.

The solution found was to remove this output capacitor and the circuit seems to still be stable at both 60°C and -40°C.

Our question is, is it not recommended to use the circuit in this configuration without this output capacitor or should we replace it with another capacitor given the circuit described here. The C9 and C10 are low ESR ceramic capacitors.

Here are some measurements and simplified schematics attached to illustrate. We can see the ringing is way less present without it.

Thank you

  • 0
    TI__Genius 12675 points

    Hi Romain, 

    Thank you for sharing this with us. 

    You mentioned that the second LDO is the one creating the glitch. 

    It does seem odd that the first LDO has higher capacitance and is not creating any disturbance in regards inrush current. 

    I also see that the First LDO generates a 3.3V and that the second one is also 3.3V, can you confirm that the input for the second LDO is higher than 3.3?

    Also, has R10 been removed to isolate this and see if the inrush is still present when there is no load? 

    In addition, I see that the second LDO is only sharing the 47uF, how far is this from the LDO? 

    Although the device seems to be stable without the 10uF ceramic capacitor, there might be a concern if there is any sort of transient (if expected) which then could make the LDO go unstable. 

    Best, 

    Edgar Acosta