TPS7A74: Schematic review and question on Css

Hi Hailiang,

1

What this statement means is that ss caps of greater value than 15nF causes the turn on of the device to slower as that is the intention. However certain customers toggle the EN pin quickly and with that would like the LDO to turn on and off quickly as well, but with a large nr/ss capacitor the discharge and charging of this capacitor slows the rate of turn on and off to a point where quick switching on the EN pin may not actually turn the device on before the EN pin switches back to off causing that input signal to be destroyed which is not ideal. In order to maintain signal integrity for high frequency EN switching applications <15nF is recommended

2

The capacitor from FB to OUT is called a feedforward capacitor. We have an app note detailing the pros and cons of utilizing a feedforward capacitor. I've linked it here. The summarized benefits are that the LDO control loop is more stable, PSRR and noise is improved, and load transient performance is more robust.

All the schematics are connected properly, and passives are sized appropriately for each of the respective output voltage options.

For F3

Utilizing the JEDEC Standard temperature values, This DC operation would push the device into operation at 145.3767C. Which is above the recommended operating temperature for the device. It shouldn't enter thermal shutdown, but during a line or load transient condition it may enter thermal shutdown due to the high power dissipation across the die and the high ambient temperature operation. This can be reduced with good board design, but it was something I wanted to call out as the device is not tested at 145C and is only characterized up to 125C. It will function up to thermal shutdown at 165C but it may not follow all EC table conditions. I've linked our thermal app note detailing how to improve thermal performance for LDO's using good layout and board design.

Regards,

John