TPS54618: Power rail Ramp dwell

Hi Dan,

Can you post or reference a waveform of what you mean?  I'm not sure that I understand.

We also have the newer, smaller TPS62867 and module TPSM82866A which are recommended over the TPS54618.

Thanks,

Chris

Hi Chris,

Here is a plot showing the start-up ramp of one of our power rails. Can see a time period where we sit around 130mV before ramping up.

Dan

Thanks for sharing Dan.  Is it possible to add the EN and PH pins to the waveform?

In FPGA supplies especially, and in other systems with multiple rails, it is common for one rail to leak back onto another through an I/O pin of the processor, etc.  That might be what is happening here.

Chris

Thanks Chris,

That was my first thought, your guess that we are supplying an FPGA is correct. I will try to get access to make some more measurements. We are seeing similar behavior on all the three regulator outputs for the FPGA rails despite sequencing them with a 1V2 core voltage coming up first and still showing this characteristic. I will get some more information on that rail to start with as i know the other rails will be disabled until that one is established.

Dan

Thank you Dan.  Yes, the measurements should help determine where this voltage is coming from.  You can also look at Vin, as there may be a path from Vin.

Chris