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TPS61085 oscillations at SWitch pin

Joe Grehan
Prodigy 40 points
Other Parts Discussed in Thread: TPS61085, TPS65186

Hi,

I have a concern about the signal I am observing at the SW pin on the TPS61085.

 my circuit has been designed to supply a maximum 200mA and I find when the load is nearing this value the signal at the switch pin is very clean (no oscillations or bumps as they are referred to in application note SLVA381 "Simplifying Stability Checks by John Stevens")

I designed the circuit using Switcher PRO software, it calculates a Gain Margin of -18dB , phase margin of 74 degrees, when I use a 10uF ceramic Capacitor on the output

However even with these low ESR capacitors I noticed when the load begins to slowly decrease over a minute or so, the oscillations starting to increase in quantity at the SW pin to a maximum when my load has reduced to 20mA (as shown)

It is not difficult to reduce the oscillations at a particular load by changing the capacitance on the output. however in practice my load is going to vary.

Is it possible to remove these oscillations for a load that varies over a range (20mA to 200mA in my case)?

Based on the attached images, are these oscillations acceptable or are there risks associated with leaving the design as is?

 

  • 0
    TI__Guru**** 150770 points

    At lighter loads, your circuit is simply going into DCM or discontinuous operation.  The inductor current is reaching zero during each switching cycle.  This is ok and unavoidable at lower loads for any non-synchronous converter.

  • 0 in reply to Chris Glaser
    Prodigy 40 points

    Thank you Chris,

    I would like to keep the  device in contineous  for as long as possible by reducing the capactance to a minimum.

    e.g. with a load of 50mA I will reduce the capactance until the device goes into contineous mode and then I will check that the output Pk-Pk on the output is acceptable at the normal 100mA load. I will then ensure the device does not overheat at a worse case 200mA .

    What should I expect to  happen on the SW pin if the load exceeds the design lout?

    Is this an acceptable approach to take to keep the device in contineous mode as much as possible?

  • 0 in reply to Joe Grehan
    TI__Guru 65200 points

    Hello Joe,

    A change in the output capacitance will not change the point where the IC reaches power save mode. Just the current in the inductor decides if the IC is in continuous conduction mode or in discontinuous conduction mode. So you are reducing the output current value reaching this point if you increase the inductance value of the used inductor, but then you also change the stability of the system. Normally it should stay stable as long as you keep the quotient L*Cout the same. Nevertheless, I would always check the stability with the simple method given in this application note: http://focus.ti.com/general/docs/techdocsabstract.tsp?abstractName=slva381

    In addition, there is the possibility to switch to TPS65186 that has the possibility to switch off the power save mode.

    Best regards,
    Brigitte