[FAQ] BQ76952: Do the DCHG and DDSG signals on the BQ769x2 follow the CHG and DSG FET driver pin states?

The DCHG and DDSG pins are multifunction pins that can be configured as outputs and are used to signal the host MCU of when a fault condition exists and the current FET driver state.

Normally, the DCHG and DDSG pins will follow the CHG and DSG FET driver states. By default, DCHG and DDSG are configured to be active-high, i.e. If CHG or DSG is logic high (1) then the DCHG and DDSG will be logic low (0).

The pins can also be configured with different outputs as follows:  Active-High, Active-Low, Tri-State, Weak-pulldown to VSS, Weak-pullup to REG18, and high drive for REG18 or REG1 as desired.

In the case where the pin is configured to be active-low, then when CHG or DSG are logic high (1) the DDSG and DCHG states will follow the state as logic high (1).  This only happens if the pin is configured by setting the PIN_FXN1 and PIN_FXN0 bits according to the pin configuration field descriptions below.  

In the following example we demonstrate active-low behavior by configuring the DDSG pin. 

DDSG Pin Config Register Field Descriptions

Bit 7 - OPT5:

• 0 (default state): selects active-high (DDSG is high when DSG is disabled
• 1: selects active-low (DDSG is low when DSG is disabled)

Note: Polarity only works when pin is configured for DDSG mode (with no effect in GPO mode)

Bit 6 - OPT4: Bit is unused

Bit 5 - OPT3:

• 0 (default state): output high drive uses REG18
• 1: output high drive uses REG1

Bit 4 - OPT2:

• 0 (default state): Weak pull up to REG1 disabled
• 1: Weak pull up to REG1 enabled

Note: Not available when OPT3 is set to be logic high (1)

Bit 3 - OPT1:

• 0 (default state): Pin drives tri-state when controlled to be driven “hi”
• 1: Pins drive active high when controlled to be driven “hi”

Note: Not available when OPT3 is set to be logic high (1)

Bit 2 - OPT0:

• 0 (default state): weak pull down to VSS disabled
• 1: weak pull down to VSS enabled

Bit 1 – PIN_FXN1 & Bit 0 – PIN_FIXN0: Configure pin using both pin states

• 00 (default) – Pin is not used
• 01 – General purpose output (GPO)
• 10 – DDSG
• 11 – ADC input or thermistor

Note: Please ensure the correct pin options are selected for desired pin behavior.

During NORMAL operation, FETs are able to be controlled manually or autonomously. However, FET control can only be initiated in either case by first setting the FET_EN bit and when the FET_CTRL_EN bit is set. This can be found in Registers tab on BQStudio in Settings:Manufacturing:Mfg Status Init[FET_EN] and Settings:FET:FET Options[FET_CTRL_EN] respectively.

Alternatively, more information about this register can be found in the device Technical Reference Manual (TRM)  Table 13-34. Mfg Status Init Register Field Descriptions.

Important Note:

To ensure fastest turn off time when using the DDSG and DCHG pins to drive low-side FETs, the following register settings must be set with the following:

In Settings:Protection:CHG FET Protections A - We recommend setting this register to 0x18 or 0x98

In Settings:Protection:DSG FET Protections A - We recommend settings this register to 0xE4

These registers can also be modified by using the Data Memory tab in BQStudio or by writing the value to the RAM address.

Configuring these protection settings to anything other than the values specified above may delay the turn off time by an unspecified amount of time but up to at most 250ms in NORMAL mode and by up to 1 second in SLEEP mode.

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