LP87702-Q1: LP87702 SW_reset issue and GPO0 delay

Ted Xu

Part Number: LP87702-Q1
Other Parts Discussed in Thread: AWR1642, TPS7A52-Q1,

Hi BU team
My customer used LP87702D-Q1+TPS7A52-Q1 to provide the power rails to AWR1642. AWR1642 would be latched off in bootloader stpe after write SW_reset bit to LP87702D-Q1 via I2C interface. Customer has below concerns to be get clarified. Customer doubted if re-startup sequencing after SW_reset configuration didn't meet the AWR1642 requirement?

1. In the description of GPO0_startup_delay in 0xC register, what's the control signal? EN1?

2. Does LP87702-Q1 share the same startup behaviors for the first startup and the re-startup after the configuration SW_reset bit? Does EN1 be toggled after the configuration SW_reset bit?

Would help share the re-startup sequencing example like the diagram in Figure 8-7 of datasheet?

Thanks

over 1 year ago

0 Niko Alatalo over 1 year ago

TI__Genius 12350 points

Hi Ted,

I am looking into this and will get back to you today.

regards,

Niko

0 Niko Alatalo over 1 year ago in reply to Niko Alatalo

TI__Genius 12350 points

Hi Ted,

1. the section 8.3.12 in datasheet gives more information on GPO control. The control can be selected with GPOx_EN_PIN_CTRL bits. The enable signal can be either EN1, EN2 or EN3 (EN2 and EN3 are multiplexed with i2c pins).

2.Section 8.3.9 tells how SW reset behaves. This resets all the registers and reads OTP memory again (all values are set to default). The bucks are enabled by the rising edge of ENx signal so the external ENx signal should be toggled after the SW reset.

Did this answer your questions?

regards,

Niko

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LP87702-Q1: LP87702 SW_reset issue and GPO0 delay