TPS6593-Q1: what is the meaning of IO+DDR and Partial IO low power mode

Hi Pengfei,

IO+DDR low power mode has all the power rails disabled except BUCK4 and BUCK5, which supply the 1.8V IO domain and DDR rails. Partial IO low power mode has all the power rails of the PMIC disabled.

From the AM62Ax Sitara Processors Technical Reference Manual (Rev. A), In Partial I/O, I/O pins and small logics in the CANUART I/O Bank are active, and the rest of the SoC is turned off. The user can use the I/O pins to aggregate multiple I/O wakeup events and toggle PMIC_LPM_EN pin to enable PMIC or discrete power solution when an I/O wakeup event is triggered. The information on the I/O wakeup event is logged in the MMR in the CANUART I/O bank and helps the software to distinguish between cold boot and wakeup to respond to the wakeup event faster.

There is currently no explanation of the I/O + DDR power mode in the AM62A TRM to explain the implementation on from the processor perspective.

Regards,
Megan