Hi,
The datasheet illustrates the device power state by the diagram below. Only LP_STANDBY is mentioned, I wonder what about STANDBY when LP_STANDBY_SEL = 0?
Hi Zehui,
The STANDBY state is one of the pre-configurable mission states of the device, and is included in the Mission States bubble further down in the diagram you have provided. The specifics of the mission states will vary with the NVM of the device. The user guide for your device will show these transitions in the pre-configurable finite state machine (PFSM) mission states and transitions figure.
For example, the user guide for TPS6594133A has the following state machine diagram, with the STANDBY state included in the PFSM:
LP_STANDBY is part of the fixed device power portion of the FSM and will not be changed between devices. This is why we are able to describe LP_STANDBY in the diagram in the datasheet for all variants of the device.
Regards,
Megan
Hi Zehui,
No problem!
1. When VCCA is valid with no WAKE request with the NVM described by the state diagram I provided, the device will stay in the STANDBY state. Even if LP_STANDBY_SEL is set to 1, the device will stay in the STANDBY state until the valid WAKE request is received.
2. Yes, INIT will be followed by BOOT BIST regardless of a valid WAKE request. The Device Start-up Timing Diagram from the datasheet shows the valid ON request is only taken into consideration once the BOOT BIST has completed.
3. Yes, BOOT BIST will be followed by STANDBY until the valid WAKE request is received. This is also shown in the Device Start-up Timing Diagram before the device transitions to the ACTIVE state.
Regards,
Megan
Hi Zehui,
I will check with my colleagues on the specifics of what happens when the device is initially powered on and the transition from the INIT state to the LP_STANDBY state.
Experimentally, I was able to find the device stayed in the STANDBY state before the first WAKE event, even when LP_STANDBY_SEL = 1. I used the TPS65941515 NVM, which has the same connections between INIT, BOOT_BIST, STANDBY, and LP_STANDBY as I have shown in the previous diagram. 
When the device was turned on with ENABLE pulled low, the device stayed in the STANDBY state with the BUCK and LDO outputs all at 0V. I measured a non-zero voltage out of LDOVINT, which meant the device was not in LP_STANDBY. I was able to write to LP_STANDBY_SEL before ENABLE was pulled high, but LDOVINT did not fall to 0V. Once I enabled the device at least once, the device transitioned to the LP_STANDBY state as expected.
According to the NVM configuration file, the device enters the mission states through the PFSM_START state and the WAIT4ENABLE state. The PFSM_START state configures the triggers, and the WAIT4ENABLE state ensures all the outputs are off while waiting for a WAKE request. This state functions the same as the STANDBY state since all of the outputs are powered off. Since I was writing the LP_STANDBY_SEL value during the WAIT4ENABLE state, that may have been why I could not experimentally start the device in the low power standby state. I will check with my colleagues to make sure. The PFSM_START state and WAIT4ENABLE are mainly referenced in the Scalable PMIC's GUI User’s Guide (Rev. B).
Regards,
Megan
