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SImulation

joe jazrawi

Prodigy 60 points

Other Parts Discussed in Thread: TPS40210

Hello. During simulation in pspice, it was noticed that TDS pin GDRV was not being toggled at the gate of FET. The simulation file sent by ti (to me) are enclosed. was needing simulation profiles for both transient startup and steady state. Thanks.TPS40210_PSPICE_TRANS.zip

over 2 years ago

0 Moritz over 2 years ago

TI__Genius 17295 points

Hello,

Thanks for reaching out. We will look into this and will be back with an answer until the mid of next week.

Kind regards

Moritz

0 Moritz over 2 years ago

TI__Genius 17295 points

Hello,

Can you send a screenshot of what is not working? For me the simulation is working and the gate signal is switching.

Best regards,

Moritz

0 joe jazrawi over 2 years ago

Prodigy 60 points

Hello, sorry Ive been a bit busy. Ill send the screen shot by this Friday. Thank you.

0 joe jazrawi over 2 years ago

Prodigy 60 points

Please close. Thank you for your support.

0 joe jazrawi over 2 years ago

Prodigy 60 points

Please close this request. The matter has been resolved. Thank you.

0 Brigitte over 2 years ago in reply to joe jazrawi

TI__Guru 67130 points

Hello Joe,

Thank you for the update. In general you could close it by pressing the button "This resolved my issue", but I have now closed it.

Best regards,
Brigitte