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100V MOSFET application question

Muhsiu Wei
Prodigy 70 points

Hi team,

I am looking at a DC/DC brick DVT report.

The VDS stress are exceed the MOSFET spec (118V > 100V) during the SCP testing. But the vendor trying to convince us by calculate the energy at short circuit protection and claim the energy smaller than avalanche energy. As I know, the designer should make all reasonable attempts NOT to operate a MOSFET in avalanche. So the VDS voltage exceed MOSFET V(BR)DSS spec is not allow. It could be causing permanent damage. 

May I learn from you, from the semiconductor point of view is it acceptable?

 How many deratings does semiconductor vendor recommend for 100V MPSFET VDS stress?

Looking forward to hearing from you. Thank you.

Muhsiu

  • +1
    TI__Mastermind 37930 points

    Hello Muhsiu,

    Thanks for the inquiry. TI does not recommend operating the MOSFET in excess of the absolute maximum ratings including BVDSS, drain-to-source breakdown voltage. However, TI does characterize, spec and test single pulse avalanche for our FETs. This information is provided to ensure the device will survive in case there is a single UIS event during a fault condition such as output short circuit. If your vendor can show you waveforms and calculations that prove a single pulse UIS event does not exceed the avalanche energy ratings in the datasheet then it should be OK. Operating the MOSFET in repetitive avalanche mode may cause catastrophic failure and/or long term reliability issues. TI cannot guarantee the reliability of our FETs if they are operated in repetitive avalanche mode. I hope this helps to answer your question. Since you have not referenced a TI MOSFET part number, I do not have more information.

    Best Regards,

    John Wallace

    TI FET Applications

  • 0 in reply to John Wallace1
    Prodigy 70 points

    Hi John,

    Thanks for your reply. I'd like learn the single and repetitive avalanche conditions definition. 

    Since the DC/DC brick short circuit protection behavior is hiccup mode.

    If the MOSFET operating into avalanche every time at the hiccup duration.

    Is that defined as single or repetitive avalanche conditions? 

    Thank you.

    Muhsiu.

  • 0 in reply to Muhsiu Wei
    TI__Mastermind 37930 points

    Hello Muhsiu,

    I contacted a colleague who was closely involved in UIS testing and creating the datasheet specs. In general, TI considers a duty cycle < 1% to be a single pulse. However, because of the potential degradation and long term reliability issues, we consider it to be just a single avalanche event. We do not have any data on how multiple avalanche events affect the FET. Therefore, TI considers avalanche during hiccup mode operation to be repetitive. Other FET vendors may interpret this differently.

    Best Regards,

    John

  • 0 in reply to John Wallace1
    Prodigy 70 points

    Thank you very much, John!