• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 62 subscribers
  • Views 171 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS3840-Q1: reset, delay

Jin-Suk Choi
Intellectual 1700 points
Part Number: TPS3840-Q1

Hi~ Team.

Customer has some issue on reset delay of TPS3840-Q1.

Do we have real measurement waveform like Figure 4 VDD-RESET timing diagram?

It may help to understand.

Thanks.

  • Former Member
    0 Former Member

    Hi Jin-Suk,

    Thank you for your question!

    Could you provide some more information about the issue the customer is seeing for the reset delay of the TPS3840-Q1?

    Figure 4 of the datasheet, shown below, shows the relationship between VDD and RESET through the startup process. A delay of t_STRT + t_D occurs while the device powers on, while delays of t_P_HL and t_D occur when RESET asserts and de-asserts respectively.

    Please let me know if you have anymore questions!

    Best Regards,

    Andrew Li