LM5060: is ther max value limitation on capactior on "gate pin"

Hi Chen,

We recommend to use gate capacitance as low as possible as it affects the turn-off response time of LM5060. 

What is the motivation to increase C1 ? is it for limiting the inrush current ?

Can you share your schematic, application use case, Cout value details 

Best Regards,

Rakesh

We recommend to use gate capacitance as low as possible as it affects the turn-off response time of LM5060. 

-0704-> You are right , And I also measure the turn-ff time to make it can full fill my design.

What is the motivation to increase C1 ? is it for limiting the inrush current ?

0704--> my motivation is for limiting the inrush current.

Can you share your schematic, application use case, Cout value details 

0704-->my design as as below, and C1 is 6.8nF now.

please prvide suggestion for me about value on C1.

thank your

Hi Chen,

Understood.. Thanks

Please limit the max value for C1 to 22nF.

Best Regards,

Rakesh

Hi Rakesh

my design is LM5060 gate pin "driving 2 MOSFET "

and Total Gate Charge Qg of each MOSFET is 88nC.

Does this over max value of C1  (22nF) ?

and if the desing value is over C1 max value. what will happen.

ex. MOSFET damage or LM5060 damage ?

Hi Chen,

22nF is for C1 which is in addition to FET Qg. As we discussed earlier, it has to tested and finalized as LM5060 does not provide FET SOA protection. For example, if you short the output the FETs will get damaged.

Best Regards,

Rakesh

If it is a new design, I would recommend to use TPS4811 or TPS1211 or LM74502H-Q1 which has better gate drive strength.

Thanks

Rakesh

my desigen concept is I can measure VDS and Ids of MOSFET to confirm working condition is in SOA

so drivig current on the gate of LM5060 is not critical.

am I right ? 

or is there any benefit for the higher gate drive strength ?

In my current design

when I turn on in 1s time.

I measure the waveform is VDS and Ids of MOSFET as below.

Vin is 24V, but VDS is have peak to 35V.and then the MOSFET is damage (VDS short)

I am wondering to know does my design is wrong ?

is there anything I can do to fix the issue.

Before FET turn-ON Vds should be equal to VIN. Why is it at 35V when VIN=24V ?  Can you add GATE resistors (4.7 Ohm) for each MOSFET and check.

If FET is within the SOA limits then driving current is not a problem else you may need to slow down the GATE to reduce inrush current (Ids). For worst case, you need to check at your max operating temperature. Also, check the FET SOA during turn-OFF for overload faults

Best Regards,

Rakesh

In my deisgn, EN is trigger by VIN with RC delay.

when EN rise to 2V, mosfet start to tunr on. then the value of Ids is rising. 

In this moment,  Vout have abnormal ring waveform. that cause VDS bemcase to 35V.

is this means SOA fail?

and the layout length of gate is aroung 4000mil ,does this cause anything wrong ?

Hi Rakesh

when Vgs start to turn on..

LM5060 have the  oscillation on gate pin.

do you know what cause this issue.

and how to solve it , thank you.

Hi Chen,

The GATE length is pretty long which can cause oscillations in the GATE loop. Can you minimize it ? Please add GATE resistors (4.7 Ohm) for each MOSFET and check.

Best regards

Rakesh

Hi Rakesh

The waveform is on- state, and Gate drivie strength is only 24 uA.  It seems weak current on gate driving stregnth.

Can you help to calrify this abnormal symptom how to happen ? 

Or do you have any doucment to descripe "GATE length is pretty long which can cause oscillations " ?

thanks

Hi Rakesh

Becuase PCB layout can not change.

Can I solve this abnormal waveform by change MOSFET.?

and which kind of MOFET you can suggest for me, 

Hi

If I set higher current limitation. then action of Gate pin is not easily active by OCP.

Do this help to reduce oscillation ?

Hi Chen,

It may help. Please test and share the results.

Best Regards

Rakesh

Hi Rakesh

I want to know the way to increase the thresold value of OCP.  

Do you suggest to increase the value of Rs or increase the value of Ctimer ?