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UCC21755-Q1: Half Bridge Configuration, VEE and DESAT

Harun
Prodigy 120 points
Part Number: UCC21755-Q1
Other Parts Discussed in Thread: UCC21750, UCC12050, UCC21551

Hello everyone,

I'm working on a half-bridge circuit with a booster using UCC21755-Q1. However, I'm having issues with the usage of VEE (Negative supply rail) and DESAT. To avoid confusion, I will try to explain the design problem I'm facing in separate sections.

DESAT ISSUE

Considering that we will be using the 2MBI300VH-120-50 IGBT module and a +15V high drive voltage, according to the IGBT's technical documentation, we require a 7~8 volt DESAT threshold. However, the UCC21755-Q1 has a 5V DESAT threshold voltage. Subtracting the voltage drop across the resistor and diode, we obtain an approximate threshold level of 3.4V. This is not sufficient.

Q1: Can you suggest a method to increase the DESAT threshold level? (Different Device Maybe)

Q2: Could you provide any design recommendations or tips?


VEE ISSUE



Obtaining a negative gate voltage for the Low-Side driver is relatively easy, but I am struggling to apply a similar approach for the High-Side. 

Q3: Can you suggest a method for applying a negative gate voltage to the high-side driver?

Q4: Do you have any suggestions or warnings regarding the design of the driver section shown in the Figure?

Best Regards,

  • 0
    TI__Expert 7573 points

    Hi Harun,

    Please find attached answers to your questions below:

    Q1: Can you suggest a method to increase the DESAT threshold level? (Different Device Maybe)

    A1: I would recommend using UCC21750 which has 9.15V typical DESAT voltage detection threshold and is also pin 2 pin with UCC21755

    Q2: Could you provide any design recommendations or tips?

    A2. We would recommend to use the DESAT calculator in the UCC217xx XL Calculator Tool available on "">www.ti.com/.../UCC21750" 

    Q3: Can you suggest a method for applying a negative gate voltage to the high-side driver?

    A3: We would recommend using a Zener diode (example provided below)

    We would recommend UCC12050 for an integrated solution

    Q4: Do you have any suggestions or warnings regarding the design of the driver section shown in the Figure?

    A4: We would recommend having an input RC filter in RST/EN pin and also a high value decoupling cap and a low value decoupling cap at VCC pin to GND. Everything else in the low side looks good. For the high side try to emulate the low side along with the recommendations and a Zener diode for negative bias/ UCC12050 (for integrated solution). Please feel free to refer to the design recommendation attached below:

    Hope this helps!

    Best,

    Pratik

  • 0 in reply to Pratik Adibatla
    Prodigy 120 points

    Hi Pratik,

    Thank you for your support.

    Thanks to your suggestion, the problem I encountered with UCC21750 DESAT has been resolved.

    I believe I also have made progress in using VEE. For the High-Side driver, I am currently planning to use a zener diode and resistor combination for VEE. However, I still have some uncertainties. I will write them down below.

    Q1: Could you review the circuit in the figure above and provide your thoughts on negative gate biasing? (I positioned the zener and resistor in separate locations to avoid trace overlap. Hopefully, it won't cause any confusion.)

    Q2: The path followed by the charging current of the High-Side bootstrap capacitors is confusing. When the Low-Side IGBT is conducting and the High-Side IGBT is in the off state, the bootstrap capacitors should be charging. If we label the charging current as I1, it should follow the path shown in the figure below. Am I mistaken?

    Q3: Can you recommend a documentation regarding negative gate biasing using UCC12050?

    Q4: Do you notice any issues with the circuit diagram related to any other aspect?

    Thanks

    Best Regards

  • +1 in reply to Harun
    TI__Expert 7573 points

    Hi Harun,

    Thanks for these interesting questions! Please find my comments below:

    Q1: Could you review the circuit in the figure above and provide your thoughts on negative gate biasing? (I positioned the zener and resistor in separate locations to avoid trace overlap. Hopefully, it won't cause any confusion.)

    A1. We would strongly recommend to check the datasheet of UCC21551 from page 31 to 33 for more insight on negative biasing.

    Q2: The path followed by the charging current of the High-Side bootstrap capacitors is confusing. When the Low-Side IGBT is conducting and the High-Side IGBT is in the off state, the bootstrap capacitors should be charging. If we label the charging current as I1, it should follow the path shown in the figure below. Am I mistaken?

    A2. Please look at the charging path below (assuming C30 is your bootstrap capacitor), as per the layout recommendations attached in my previous response we would recommend making COM as your PGND

     

    Q3: Can you recommend a documentation regarding negative gate biasing using UCC12050?

    A3. The best recommendation would be the datasheet of UCC12050.

    Q4: Do you notice any issues with the circuit diagram related to any other aspect?

    A4. For Negative Bias with Zener Diode on Iso-Bias Power Supply Output, the Zener should be placed between High side source and VEE and in case of Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path the below is recommended (more details can be can be found in UCC21551 datasheet page 32):

     

    Please refer the schematic and layout recommendations attached below:
    UCC21750_Schematic_Layout Recommendation(1).pdf

    Hope this helps!

    Best,

    Pratik