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TPS36-Q1: About Manual Reset

Yuya Shoji
Expert 5520 points
Part Number: TPS36-Q1

Hi team,

I have a question.

Section 8.3.3 explains that when the MR pin is set to the Low level, the reset pin is also set to the Low level. In this case, will WDI monitoring be ignored and either t_WC or t_WO cleared to 0?

Best Regards,

Shoji

  • 0
    TI__Genius 9880 points

    Hi Yuya,

    The RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold.

    WDO output is asserted only when watchdog timer error is detected.

    So RESET  has higher priority than WDO error. If RESET is asserted when WDO is asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin is deasserted and startup delay frame is terminated.

    And the device resumes watchdog related functionality only after the supply is stable and the tD time duration has elapsed.

    Best Regards,

    Sila Atalar

  • 0 in reply to Sila Atalar
    TI__Expert 5520 points

    Hi Sila,

    Thank you for your reply. I'd like to confirm three points.

    Sila Atalar said:
    watchdog is disabled

    For WDI, WDI is ignored as this table shows, right?

    As far as I saw this diagram, MR pin is behaves as if it was V_DD because t_WC starts after t_D and t_SD terminated, right?

    The difference between WD_EN and MR is whether it contains t_SD, right?

    Best Regards,

    Shoji

  • 0 in reply to Yuya Shoji
    TI__Genius 9880 points

    Hi Yuya, 

    1) For WDI, WDI is ignored as this table shows, right?

    • When watchdog is disabled or not acceptable, WDI is ignored. 

    2)  As far as I saw this diagram, MR pin is behaves as if it was V_DD because t_WC starts after t_D and t_SD terminated, right?

    • MR  (manual reset) is an  active low pin, which mean the circuit is reset when the this pin is driven low. 
    • There are 2 condition can cause a reset. One is Vdd goes under the threshold or MR pin is asserted. After these conditions goes high again, as you said,  t_WC starts after t_D and t_SD terminated.

    3) The difference between WD_EN and MR is whether it contains t_SD, right?

    • If there is an WD_EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation.
    • The moment it's enabled, the device immediately enters tWC frame and start watchdog monitoring operation.

    Best Regards,

    Sila Atalar