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LP876242-Q1: How to access registers after GPIO2 configured as TRIG_WDOG?

Part Number: LP876242-Q1
Other Parts Discussed in Thread: TIDA-020047

Hi Experts

When LP876242 WD is enabled, we can use a pulse on GPIO2 to feed the dog in trigger mode。

1. Since GPIO2 is selected as TRIG_WDOG, SPI interface is in lack of CS_SPI,   how to access registers via SPI at this moment?

2. Can I access register via SPI  and then switch to I2C during runtime?

Thanks

Ken

  • Hello ken,

    With current NVM LP876242B0RQKRQ1 it isn't possible since GPIO2 is configured as CS_SPI and that is the only possible option to feed WD in a trigger mode. Another is GPIO4 but that is used for enable so that is not the option. So, only solution I see to have custom NVM in which I2C is configured instead of SPI and then with that GPIO2 configured as TRIG_WDOG. 

    Why do there is need for such change?

    Best regards,

    Ishtiaque Panhwar

  • Hi Ishtiaque

    Customer would like to use I2C and WD trigger mode concurrently to simplify GPIO setup and WD programming.

    There are also several threads in which I2C version is asked by other customers.  I assume that them are seeking due to the same reason.

    Thanks 

    Ken

  • Hi Ken,

    Yes, there could be requirement from the customers but we have to create a new NVM based on the business case sufficient enough to make the new one. 

    We can support I2C and WD trigger mode configuration. Can you share the customer business details via email (i-panhwar@ti.com)?

    Also would like to know are they using AWR22xx and TPR12 in their for cascade application?

    Best regards,

    Ishtiaque Panhwar

  • HI Ishtiaque

    Yes, they are following TIDA-020047 cascade HW design.

    Will check the business detail and send you email. 

    Thank you

    Ken

  • Hi Ken,

    Thanks for the information. Look forward for the business information. 

    However, at the moment customer can implement Q&A WD with existing NVM. 

    Best regards,

    Ishtiaque Panhwar