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BQ25504: Not coming out of cold start as expected

Part Number: BQ25504
Other Parts Discussed in Thread: BQ25570

We're having a bit of trouble getting the BQ25504 to come out of cold start properly. We have a low power bluetooth design (schematic attached) powered from the BQ25504 which is charging a 220F 3.8V supercapacitor connected to P2. The system seems to get stuck in cold start, with the load off, even with a fully charged supercapacitor until we shine a really bright light on the panel. Then after an indeterminate time from 10s of seconds to 10s of minutes cold start ends and normal charging operates, the system is able to operate in normal daylight and charge the supercapacitor.

We've done some scope measurements (attached) with connecting a bench supply in place of the panel and a 220u in place of the supercap to check if the circuit is operating correctly - key: 

Trace A: VS and VBAT with the same 0ref on the scope, i.e. they are more or less identical after the PFET is switched on.
Trace B: VSOL drops as the board works to recover VS.
Trace C: probably misses some of the switcher spikes with that timebase.
Trace D: Not entirely sure what VRDIV is doing here.

Notes from our test engineer:
"here are some scope traces from the solar system. I've fitted a 220uF OSCON cap and left the supercap disconnected. I bring the board into life by connecting a bench supply to VS and raising it slowly from 0V. When it reaches about 1.8V the VRDIV pin starts pulsing at 555 Hz. After I disconnect the bench supply, VS gets pumped up to >3V. The processor is programmed with live code so once it's running it wakes up every 1500ms and runs the receiver for 52ms before going back to sleep, causing VS to dip rapidly to about 2.2V every 1500ms as current is pulled, and then recover to >3V within ~60ms. The solar panel is facing the window, and if I put my hand over it the voltages fall and everything stops. "

We've checked for solder flux residue affecting the operating values and this seems to be ok. 

Do you have any hints as to why we might be seeing this and how we could resolve it? Current theories - panel is too small (although by the calculation spreadsheet we should have about 2x the minimum area), supercap is too large for the application, device isn't operating at the required levels (VBAT_UV is set too low at 1.7V instead of 2.2V but we think this shouldn't have an impact on what we are seeing). Should we be using a diffferent device? I've seen comments that the BQ25570 would be more suitable?

Thank you

.Print Schematic.pdf

  • Sorry, looks like the labels were missed off the traces:

    Trace A: VS and VBAT with the same 0ref on the scope, i.e. they are more or less identical after the PFET is switched on.


    Trace B: VSOL drops as the board works to recover VS.


    Trace C: probably misses some of the switcher spikes with that timebase.


    Trace D: Not entirely sure what VRDIV is doing here.

  • Hi Karl,

    Thank you for all the information you've provided. I have a few questions to further clarify the situation.

    I bring the board into life by connecting a bench supply to VS and raising it slowly from 0V.

    - At this point is the panel connected to V_SOL? The Voc of the panel provided in the schematic of 2.76 V which should be sufficient for the device to be enabled without supplying 1.8V to VS manually.

    - Can you confirm V_SOL before 1.8V is applied and how much if any current is being pulled? Additionally, can you provide a capture of VSTOR over time before V_SOL is applied.

    The system seems to get stuck in cold start, with the load off, even with a fully charged supercapacitor until we shine a really bright light on the panel.

    -How much current is expected to be drawn with the load off?

    -The system will typically be in cold start until VSTOR is brought up to the typical 1.8V from the input boost. This tells me that either the power drawn from the PV is small or there is a draw on the VSTOR capacitors that is preventing 

    Trace D: Not entirely sure what VRDIV is doing here.

    VRDIV is generating the reference voltage for VBAT_OV and VBAT_OK. This is done at a low duty cycle to reduce current consumption. Section 8.3.5 of the datasheet ("Nano-Power Management and Efficiency") describes this behavior in a bit more detail.

    Trace C: probably misses some of the switcher spikes with that timebase.

    This behavior is unexpected. Is there a difference between Trace C and Trace B to cause these spikes? They seem to indicate that VIN is going much higher and much lower than expected.

    Best Regards,

    Juan Ospina

  • Hi Karl,

    VBAT_UV needs to be set higher than 

    Assuming you use VBAT_OK to turn off your system load, with VBAT_UV less than 1.95V, the charger will always return to cold start when the voltage drops below VSTOR_CHGEN.

    Regards,

    Jeff

  • Hi Jeff, no we don't use VBAT_OK at all. Do we need to?

  • Hi Karl,

    The intent of VBAT_OK is to enable/disable the system load (or a series FET from the VSTOR to the system load) only when the battery is good so that VSTOR does not collapse into cold start.

    Regards,

    Jeff

  • Thanks Jeff - we're doing internal monitoring of the supply and going into deep sleep if it's below a threshold above VBAT_OK which should cover that. It's struggling to come out of deep sleep with a fully charged capacitor so we think it could be to do with the VBAT_UV setting as you've suggested. 

    best wishes

    Karl