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UCC27211A: Gate driver output still present after VDD UVLO

Part Number: UCC27211A

Hi TI team,

 

I have a typical H-bridge for a switching converter with two UCC27211A (one for leading/lagging leg) sharing the same Vdd. We are intentionally using the UVLO function to prevent switching by reducing the Vdd from 12V to 6V when the PCBA is in a reset state. I expect that when Vdd is 6V, there should be no output PWM from the gate driver since the output will become Hi-Z.

 

However, during my testing, when the Vdd is 6V and my DSP is driving the input PWM, I see that the gate driver output occasionally turn on. Please see the attached scope shots:

Zoomed in:

I am aware that there is some hysteresis + component variation based on the data sheet here:

https://www.ti.com/lit/ds/symlink/ucc27211.pdf?ts=1689125521411&ref_url=https%253A%252F%252Fwww.google.com%252F

I have 3 questions:

 

1. Is the UVLO turn off threshold threshold after the gate driver chip is turned on equal to Vddr - Vddhys = 6.5 (typical)?

2. Is the noise seen in these scope shots sufficient to turn on the gate driver for a short duration?

 

3. Our existing PCBA can only reduce the Vdd to a minimum of 6V so we will not be able to cover the entire range of component variation on Vddr lockout threshold. Could you provide the distribution curve of what the min/typ/max spread looks like for this parameter?

 

 

Thanks,

 

Rick

  • Hello Rick,

    I looked at some temp characterization data on this device and I see that at cold temperature the VDD turn off UVLO is lower, closer to 6.2V with a room temp of ~6.4V and hot of 6.5V. We will not be able to post detail test data on a public forum. I see some high frequency content (ripple) on VDD, and with being not too far away from the thresholds there may be a possibility of triggering UVLO  from noise. Is there any other possible means of disabling the driver? Stopping or interrupting the PWM inputs would be on method as well.

    If you need more detailed data, we could communicate privately by requesting to friend me on the E2E forum.

    Regards,

  • Hi Richard! Thanks for your reply.

    For question #1, could you confirm my understanding of this parameter? The way I understand it is, if the gate driver is already ON, then the VDD required to trigger UVLO would be 6.2V (min) minus 0.5 (hyst) resulting in 5.7V. Assuming worst case conditions.

    Or is the number you mentioned in your answer already including the hysteresis and the hysteresis is for turn ON? And therefore the VDD threshold for turn off is 6.2V worst case.

    For question #2, with the high frequency spike on VDD, how long does the gate driver stay on? The probe shows the spike is only for a ~2us and then the VDD returns to steady state of 6V. Do you have more details on the timing for setting/clearing UVLO? Is there any internal filtering for this?

    For question #3 - I sent you a friend request for more details.

    Is there any other possible means of disabling the driver? Stopping or interrupting the PWM inputs would be on method as well.

    Yes, normally we will stop PWM, or rely on pull down resistors in PCBA reset state. However, under some secondary fault scenarios where the previous mechanisms do not work, this UVLO behavior is needed to cover a corner case issue that was found.

  • Hi Rick,

    Thank you for the most recent plot, it is interesting that the output seems to show every other pulse output response. You have a point in the 500mV hysteresis from the stop to the start point. The spec I noticed that would have me concerned is the 6.2V minimum rising threshold (start) when you pull VDD low to 6V.  This makes me think that worst case to guarantee a stop, worst case you need to get below 5.7V.

    Is it OK if I close this thread and we communicate on the private message? I did see the friend request. You can always get back on and reactivate this thread if desired.

    Regards, 

  • Sure, we can communicate in private message. Need you to accept the friend request so I can start a conversation with you

  • Hi Rick,

    I am closing this thread as resolved as we will continue on the private communications.