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TLV809E: Test conditions for "tD Release time or reset timeout period"

LIN
Intellectual 410 points
Part Number: TLV809E

The specifications for tD - Release time or reset timeout period for , e.g. Variant A, is 130ms to 279ms.

1. Is this guaranteed over operating temperature range and operating voltage range?

2. Note 2 below the table in Section 7.6 indicates "VDD: (VIT--10%) to (VIT+ + 10%)". What does this mean?

Thanks.

  • 0
    TI__Prodigy 90 points

    Hello,

     

    1. Yes, the reset timeout period is guaranteed over our recommended operating temperature range and operating voltage range on the datasheet.
    2. This note indicates that VDD is in the range of 10% below VIT- (input threshold voltage) and 10% above VIT+, where VIT+ = VIT- + VHYS. The following diagram in Section 7.7 provides a nice visualization of what VIT- and VIT+ mean. For instance, when the input voltage drops below VIT- , a reset is asserted. The device does not de-assert until the input voltage rises above VIT+ and a duration of tD (reset timeout period) has passed.

     

     

     

    Best,

    Allison Kuo