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LM5123-Q1: tDHL too lower than spec 20ns

Sway Chen
Prodigy 165 points
Part Number: LM5123-Q1
Other Parts Discussed in Thread: LM5123EVM-BST

Hi TI experts,

Question 1: Vgs turns hi already, but the Vds still kept hi, too. It makes me have poor efficiency and superheat. If TI experts can help me out with this, I will appreciate it.

Question 2: I noticed the tDHL in spec needs 20ns at least. However, I overlap the Hi side and low side gs signal and the measured value is 9.1ns. I have no idea if it is correct. (waveform2) The phenomenon doesn't show up on the hi side mosfet turning on. (waveform3)

Thanks a lot ~

test condition:

Vin=24V

Vot=54V @ 3A

fsw=200kHz

Sway

waveform1:

waveform2:

waveform3:

sch1:

  • 0
    TI__Mastermind 23570 points

    Hi Sway,

    Thanks for reaching out to us via e2e.

    It is a bank holiday today. Please expect a response by Wednesday.

    Best regards,

    Feng Ji

  • 0 in reply to Feng Ji
    TI__Mastermind 31580 points

    Hi Sway,

    Sorry for the long delay.

    Question 1: The schematic shows that there are 10 Ohm resistors at each gate. These might be to high, which affects the discharge of the FETs, leading to a lower actual dead-time than regulated by the device.
    I would recommend to reduce the gate resistance of both FETs to max 5 Ohms and check if the behavior improves.

    Questions 2: Are you measuring the gate voltages directly at the FET, or directly at the IC pin?
    If the measurement was taken at the FET, it can show that the dead-time is lower, as the low side FET is not fully discharged due to the voltage drop at the gate resistor, while the high side FET already turns on.
    To clarify this, you can make a measurement directly at the IC pin and check if the dead-times are like specified in the datasheet.

    Thanks and best regards,
    Niklas

  • 0 in reply to Niklas Schwarz
    Prodigy 165 points

    Hi Niklas,

    Question 1: All of the measurements are tested at FET directly. I tried the 4.4ohm even lower value resistor on my circuit, but the system became unstable. If any solution can improve this problem I will be grateful.

    Question 2:The photo below shows the measurement at LM5123EVM-BST, with a slight overlap at gs and ds, even when using 0ohm. It's unclear if only the measurements on the IC side and FET side differ.

  • 0 in reply to Sway Chen
    TI__Mastermind 31580 points

    Hi Sway,

    Thanks for the update.

    As you mentioned the design becomes unstable with lower gate resistance, I looked at the schematic in general and found some design improvements.
    - An inductance of 6.8uH is rather small for this design and will lead to larger current ripple and more stress on inductor and FETs.
    I would recommend an inductance in range of 15uH - 30uH.

    - The compensation network is uncommon for this topology. Common type II compensation use one HF cap from COMP to GND and one RC combo from COMP to GND as well.

    To optimize stability, we offer a quickstart calculator tool:
    https://www.ti.com/tool/download/SLVRBJ1
    I would recommend aiming for at least 60 degree of phase margin.

    Improving the design should have a positive influence on the efficiency and should reduce FET overheat as well.

    Best regards,
    Niklas