TPS6594-Q1: How to release the EN_DRV

Hello Zhihua,

If all connections are correct then when you boot up and the enable is high.

Do this:

1. Read INT_TOP (0x5A)
   1. Handle all interrupts excluding INT_STARTUP
2. Set your NSLEEPB[0] & NSLEEPB[1] bits in register FSM_NSLEEP_TRIGGERS (0x86) to 1
   1. In short (Write 0x03 to REG:0x86)
   2. Clear the interrupt for INT_STARTUP (Write 0x02 to REG:0x65)
3. If the Watchdog is not currently long window or disabled, write 0x01 to REG:0x80 
   1.  See section 8.7.1.193 WD_THR_CFG Register (Offset = 409h) [Reset = FFh] for more information on the "If" statement
      
      1. The datasheet that contains the above section: TPS6594-Q1 Power Management IC (PMIC) with 5 BUCKs and 4 LDOs for Safety Relevant Automotive Applications

The reason why the PMIC "turns off" is because it's going into a low power mode, the device should be able to read INT_TOP.

If there was a genuine power issue register INT_TOP should be able to notify you if that occurred. The sleep bits are part of the triggers for the transitions.

See the Figure 6-1. Pre-Configurable Mission Finite State Machine (PFSM) States and Transitions in the user guide below.

The information on the state transitions are in the User's guide (link): User’s Guide TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto 7 J721E, PDN-0B

Lastly, if the watchdog is not in the correct state you will not be able to arbitrarily drive the EN_DRV pin through the register 0x80.

Hope this helps,

Nicholas