TPS65150: No delay and no VGH output?

Hi Mark,

Have you captured the waveform of GD?

And have you tried to connect the second charge pump to DRVP and DRVN instead of the SW node?

BR

Patrick

Unfortunately - since we're not using GD, we did not put a pullup on it... so it is low all the time.

If you refer to the Rev 1.1 schematic, you can see the second charge pump for VGH was originally both connected to DRVP - we had no VGH output before the rework.

I can try moving the second charge pump on VGL to DRVN and see if the output reaches the target voltage of -13V.

Did you see any issue with the Rev 1.1 schematic?

Hi Mark,

Schematically it seems good. If the load is disconnected, will the voltage rails ramp up successfully?

BR

Patrick

If I connect the second charge pump to DRVP, I do not get full voltage out of D5 (i.e. CPI) , and if I connect second stage to DRVN, no output at all on VGL

No - they go up and overshoot, then slowly drop off to zero - we still do not get anything out of VGH pin (CPI goes to almost 20V)

Hi Mark,

Ok, may I know if IC will start up successfully if only one stage of charge pump connected? And you can try decreasing the VGL to -12V or lower to see if this will help.

BR

Patrick

I removed the FDLY cap and shorted to VIN to remove the fault checking and the VGL eventually reaches -13V... still nothing OUT of the VGH pin.

You can see how the VGL changes in two distinct, long delayed steps. I'm sure this delay in reaching the target -13V is the reason the part shuts off?

And why are we nod getting anything out of VGH (with CPI @ 15V)

With fault checking disabled, we now have all 3 outputs working, BUT not at the right timing - see the waveform above) - can you check my capacitor values for the desired timing delays? 0.22uf for ~20ms - is this correct?

Hi Mark,

Could you please clarify what C1~C4 represent in the waveform? 

And may I know how many boards have you tested? Will this issue be reproduced on every board? Thanks

BR

Patrick

C1 is not used

C2 is AVDD (set to 8.2V)

C3 is VGL (set to -13V)

C4 is VGH (set to 15V)

Why does VGL immediately drop to ~7.5V for ~45ms before going to the desired -13V?

We have tested 2 boards with identical results. We have a 3rd board not yet powered up.

Desired timing/delays are as follows;

FDLY has 0.1uf for ~45ms delay (removed and connected to VIN to get latest results)

DLY1 has 0.22uf for ~20ms delay AVDD-to-VGL

DLY2 has 1000pf for ~1ms delay VGL-to-VGH

Are these capacitor values correct for the desired timings?

Hi Mark,

Please allow me some time to check, thanks

BR

Patrick