UCC28701: APPLICATION FOR 600V TO 1000V BIAS

Hi Robin,

Thank you for the query on PSR flyback device.

Yes, UCC287xx family of devices can be used for this application. UCC2870x devices does not have HV startup integrated. So if there is a spec for standby power , you might have to go for the HV JFET integrated startup with devices like UCC2871x series or UCC28730.

I was able to find a reference design using UCC28700 device close to your spec.

https://www.ti.com/tool/PMP10415

My only concern is 1200V switch will be too close for 1000V input voltage condition. Even with a suboptimal turns ratio (where you will limit your duty cycle and affect efficiency by choosing a relected voltage close to 100V) and have a well designed transformer, there will barely be 15% margin at most on the switch. We do have a couple of reference designs with 1000V input but ended up using 1700V SiC.

 You can see the results here:

https://www.ti.com/lit/ug/sluucn1c/sluucn1c.pdf?ts=1693635444913&ref_url=https%253A%252F%252Fwww.google.com%252F

We do have TINA simulation model for this IC:

https://www.ti.com/product/UCC28700#design-tools-simulation

Please let us know if you have further questions.

Regards,

Harish

Hello Harish:

Appreciate the information you provided.

What do think of the "2-level" flyback design using UCC2870x controller- mentioned in Wolfspeed  Ref design bt not pursued & also in ST Micro with example.?

Then the switch rating gets to half the input max.

Others have stated it to be equal to the max but that cannot be true with diodes clamping to input or to Return. In OFF condition, diodes come in series across Vin-GND in this topology.

I would like to email you the approach for your comments if I can get your email address.

The approach is well documented though yet ours is "unique" in many respects.

Our intention is to make a product out of it & not confined to a mere curiosity.

r

Hi Robin,

Thank you for the reply.

By two level, I assume a two switch flyback. Please correct me if I am wrong. The only disadvantage I see with this topology is the high side side driver requirement and limiting the duty cycle to 0.5 (but latter should not be a concern).

There is a TI document which might also be helpful.

https://www.ti.com/lit/an/snva716/snva716.pdf?ts=1693897034954&ref_url=https%253A%252F%252Fwww.google.com%252F

Please email the documents to harish.ramakrishnan@ti.com

We can definitely have a look at it and provide our comments. All the best with the design.

Regards,

Harish