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TPS563200: IC Gets Damaged for Minimum Load of 500mA

Part Number: TPS563200

Hi Team,

We have designed a 12V2A to 5V3A board using the WeBench. 

When we start testing the assembled PCB, we notice that even for a minimum load of 5V3A, the IC is getting damaged.

Below is the schematics suggested by WeBench and we have implemented the same.

We need your expertise in resolving the design.

Regards,

Sadashivan

  • Hi Sadashivan,

    What do you mean 'damaged'? Does the High-side FET short (VIN short to SW) or Low-side FET short (SW short to GND)?

    Could you please share the layout file for review?

    Do you have some test waveforms for us to check?

  • HI Athos,

    Thank you for your response.

    I have attached the schematics and layout in PDF format.

    Schematics and Placement

    We are seeing a short between the:

    1) SW and GND Pin. Our understanding Low Side FET

    2) SW and VIN Pin. Our understanding High Side FET.

    Regarding the application, the end application is a camera. However, right now we are testing with the Lab Power Supply and Lab Programmable Load.

    These are certified and calibrated lab equipments, as we use them for many of our product developments.

    Regards,

    Sadashivan

  • Hi Sadashivan,

    For FET short cases, there's usually voltage stress on the MOSFET and possibly related to the layout.

    The schematic looks good. Regarding the layout, the GND pin should be covered with large copper island but not a singe trace.

    This may cause the large parasitic inductance on the GND trace and the SW would have a high ringing when the High-side FET on.

    You can check the SW waveform using full bandwidth probe to see if the spike has risk that the voltage is over 19V.

    To modify the layout, you should follow our datasheet especially the input and GND.

  • HI Athos,

    Thank you for your suggestion. We have rerouted our PCB as per the suggestion and the circuit is working fine.

    Regards,

    Sadashivan