This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC28C56H-Q1: Questions about UCC28C56EVM-066, (doc bumber sluucn1c)

Part Number: UCC28C56H-Q1
Other Parts Discussed in Thread: UCC28C56EVM-066,

Questions about UCC28C56EVM-066, (doc bumber sluucn1c)

1. Q1, Q2 form HV startup for VDD, but zener D5 to Q2's gate, can not be breakup to generate a voltage of 25V. so what is the current path of D5?

2. Since voltage of VDD exceed 18V, VREFof UCC28C56H-Q1 powered up to be 5V, which trun on Q3, pull gate of Q2 to HV_GND, and finally turn off Q3.

    HV Startup should be trun off, when AUX supply work normally. If Vref powered up to be 5V, before AUX supply work, HV startup was turned off, and take UCC28C56 into power down, and then power up.

    This will not work probably.

3. Checking  out BOM of this EVB, and I found some component can't be found on Schematic. U2, U3 for isolated feedback, can be found on BOM list, but there are no U2 or U3 on Schematic.

    Where can i found complete Schematic?

4. What is the fuction of Leading Edge Blanking, and how can it work?

  • Hi Bobo,

    I will take care of this thread and I will be back to you soon today.

  • Hi Bobo

    1. Q1, Q2 form HV startup for VDD, but zener D5 to Q2's gate, can not be breakup to generate a voltage of 25V. so what is the current path of D5?

    D5 function is to prevent that the gate of Q2 exceeds 22V. Q1 and Q2 are not normal switch MOSFETs but Depletion Mode MOSFETs. Meaning that they will act as current sources when their Vgs voltage reach a negative value threshold (around -1V in this case). At the beginning of the start-up, D5 will be off and the current going through R5 will be determined by the forward voltage of D9, Vgs voltage of Q2 and R5 resistance value.

    2. Since voltage of VDD exceed 18V, VREFof UCC28C56H-Q1 powered up to be 5V, which trun on Q3, pull gate of Q2 to HV_GND, and finally turn off Q3.

        HV Startup should be trun off, when AUX supply work normally. If Vref powered up to be 5V, before AUX supply work, HV startup was turned off, and take UCC28C56 into power down, and then power up. 

    Q3 is a normal switch MOSFET and its function is to turn off HV start-up after VDD has reached the UVLO value (18.8V) and after Vref reaches 5V. When Vref reaches 5V, Q3 turns on and clamps Vgs voltage to -18V and turns off Q2 (depletion mode MOSFET) and therefore it turns off the HV start-up.

    For more details on HV Start-up please refer to Section 9.2.2.12 of Datasheet or the article pointed out at the bottom.

    3. Checking  out BOM of this EVB, and I found some component can't be found on Schematic. U2, U3 for isolated feedback, can be found on BOM list, but there are no U2 or U3 on Schematic.

        Where can i found complete Schematic?

    U2 and U3 are not populated in the Schematic, that is why the Quantity in the BOM specified for these devices are zero. They probably come from another version of this EVM topology, but they are not part of this EVM's schematic.

    4. What is the fuction of Leading Edge Blanking, and how can it work?

    The function of Leading Edge Blankign is to pull down the CS voltage each time the MOSFET is turned on. This is to prevent a high peak voltage at the CS pin, which would lead to an early turn off of the MOSFET. The period of time the Leading Edge Blanking is activated (this must be shorter compared with switching period) depends on C23, R26 and R27.

    For more details on Leading Edge Blanking, please refer to Section 9.2.2.13 of Datasheet.

    Datasheet: UCC28C5x-Q1 Automotive Low-Power Current-Mode High-Performance PWM Controller for Si and SiC MOSFETs datasheet (Rev. C)

    Detail HV-start up: High Density Auxiliary Power Supply Using a SiC MOSFET for 800-V Traction Invert

  • Hi Manuel,

    I thought start up of UCC28C56 should be like this:  HV start up and VDD reaches UVLO ---> Vref reaches 5V ---> OUT generate PWM for Q5 ---> AUX power for VDD take works ---> trun off HV start up.

    On the EVM, is there any risk that Vref reaches 5V, and turn on Q3 to turn off Q2, before OUT can generate PWM for Q5? If OUT can not output PWM, there will be no aux power for VDD. At this time, HV start up was turned off. so UCC28c5x will be power down.

    Is UCC28c5x suitable for High voltage 1500V maximum? If not, what is your suggestion?

    Thanks!

  • Hi Manuel,

    1) On active start-up circuit, if I choose a large value of resistor from Vin to Collector of Q4, can I change Q4 to a regular transistor besides Dalingtion transistor?

    2) Using depletion mode MOSFETs, see below picture, maxim power dissipated by Q1 = (Vin_max - Ve_Q1) * Idd = (1000 - 521)*1.3mA = 622.7mW.

    maxim power dissipated by Q2 = (Ve_ Q1- Ve_Q2) * Idd = (521 - 23)*1.3mA = 647.4mW.

    I thougt power dissipated of Q1 and Q2, is much too large for a SOT-23 package.

    3) why is current source designed to 1.3mA?  I thinks current source should take Iout into consideration. 

    4) From datasheet of UCC28C56H-Q1(9.2.2.1), to caculate Ton_est, there is a duty cycle of 0.8(Dvin_min). What is the relationship of Dvin_min witch input voltage or output voltage?

    5) From datasheet of UCC28C56H-Q1(9.2.2.4), to caculate Ipri_rms_max, there is a Dmax, what is the relationship of Dmax with in/out voltage? 

  • Hi Bobo, I will take care of this question and reply back to you soon today. Thanks

  • Hi Bobo,

    I thought start up of UCC28C56 should be like this:  HV start up and VDD reaches UVLO ---> Vref reaches 5V ---> OUT generate PWM for Q5 ---> AUX power for VDD take works ---> trun off HV start up.

    Yes, this logic sequence is correct.

    On the EVM, is there any risk that Vref reaches 5V, and turn on Q3 to turn off Q2, before OUT can generate PWM for Q5? If OUT can not output PWM, there will be no aux power for VDD. At this time, HV start up was turned off. so UCC28c5x will be power down.

    When Vdd reaches Vddon (UVLO), the device will generator PWM output pulses and Vref=5V. It means that Q3 will pull down Q2 and turn off HV start-up after the device generates driver signals.

    Is UCC28c5x suitable for High voltage 1500V maximum? If not, what is your suggestion?

    The EVM is designed for Vinmax=1000V. If you want to increase Vinmax you can do it but the design of the components and the entire system will change: HV start-up (probably one more depletion MOSFET needed, zener diodes), Cin input capacitor, Transformer design, main switch MOSFET Q5, clamp, among others.

  • 1) On active start-up circuit, if I choose a large value of resistor from Vin to Collector of Q4, can I change Q4 to a regular transistor besides Dalingtion transistor?

    The maximum value of the collector resistor is set by Rc,max (equation 1 of App. note), at low Vin and consider a maximum startup time (tssmax). If you use a higher value for Rc than Rcmax, the soft-start time would be too large and without the limits when the device turns on at lower Vin. 

    2) Using depletion mode MOSFETs, see below picture, maxim power dissipated by Q1 = (Vin_max - Ve_Q1) * Idd = (1000 - 521)*1.3mA = 622.7mW.

    maxim power dissipated by Q2 = (Ve_ Q1- Ve_Q2) * Idd = (521 - 23)*1.3mA = 647.4mW.

    I thougt power dissipated of Q1 and Q2, is much too large for a SOT-23 package.

    Q1 and Q2 are designed for HV start-up and they should not consume a lot of power.

    3) why is current source designed to 1.3mA?  I thinks current source should take Iout into consideration.

    1.3mA is the current charging capacitor Vdd at the start-up, you can increase or decrease this current decreasing or increasing R5 value. R5 does not depend on Vin (equation 29 of Datasheet), so you can decide how fast you want to start your converter. That equation for Iout is the output current of the device to drive the main switch, it is different than the start-up charging current. There is no relationship between both.

    4) From datasheet of UCC28C56H-Q1(9.2.2.1), to caculate Ton_est, there is a duty cycle of 0.8(Dvin_min). What is the relationship of Dvin_min witch input voltage or output voltage?

    Din_min is the duty cycle at minimum input voltage Vin_min. At Vin_min, the converter needs to provide more current at the input to provide the same amount of power to the output, then the duty cycle will increase. 

    5) From datasheet of UCC28C56H-Q1(9.2.2.4), to caculate Ipri_rms_max, there is a Dmax, what is the relationship of Dmax with in/out voltage? 

    Dmax is the maximum duty cycle the converter can generate, this happens when the output is shorted (FB=0) or when the converter is starting-up. This value is specified in section 7.5 pg. 8 of Datasheet.

    If you have any Furter questions, let me know replying to this thread.

  • Hi Manuel,

    1) Why Dvin_min is 0.8? 

    According to Voltage-Second theory,  Vin *Ton = (Vo+Vf) *Nps *Toff.  Ton is duration when MOSFET drivers on, and Toff is duration when MOSFET drivers off.

    So Vin * Duty_cycle =  (Vo+Vf) *Nps *(1-Duty_cycle ), and Duty_cycle = (Vo+Vf)*Nps / [Vin + ( (Vo+Vf)*Nps)] .

    When Vin is 40V, and Vo is 15V, Vf equals 0.6V, different Nps will cause different duty cycle, see the table below.

    Since Nps is uncertain at first, I think duty cycle can not be determined for 0.8.

    Vin Vo Vf Nps Duty_cycle
    40 15 0.6 10.3 0.800677696
    40 15 0.6 8 0.757281553
    40 15 0.6 6 0.700598802
    40 15 0.6 4 0.609375
    40 15 0.6 2 0.438202247
    40 15 0.6 1 0.28057554

    2) If input voltage is 1500V, a single SiC-MOS (maxim Vds of 1700V) in flyback topology will be easilly break down when mosfet is turned off.

    What is your suggestion? Is there any reference design for 1500 Vin system?

  • Hi Bobo,

    1) Why Dvin_min is 0.8? 

    This is a Flyback working in DCM, so the volt-second balance equation is the following:

    Vin*D=(Vout+Vf)*Nps*D2

    Where D2=1-D-D3 and D3 is the time where both devices are off.

    To calculate D value you need to also consider the charge balance of the capacitor. With both equations you will get this equation for D:

    D=(Vout+Vf)/Vin*sqrt(2*fs*L/R)

    2) If input voltage is 1500V, a single SiC-MOS (maxim Vds of 1700V) in flyback topology will be easilly break down when mosfet is turned off.

    What is your suggestion? Is there any reference design for 1500 Vin system?

    In a Flyback converter, the voltage across the MOSFET during the demagnetizing time (MOSFET off) is Vin+(Vout+Vf)*Nps, so your MOSFET needs to be rated for a voltage greater than that value (I would recommend at least 30% greater). Note please that we also need to consider the clamp voltage, which is conducting for a very short time compared with the switching period (see attached). In the case of the EVM, Vinmax=1000 Nps=10 Vf=1V (approx.) Nps=10 (approx.) so a 1700 MOSFET is good enough. Fir Vin=1500, A 1700 would be short. It is difficult to find a MOSFET with a rated voltage higher than 1700 in the market. To do that you need to stack multiple FETs and you need more complex driving techniques. 

    If you have any further questions let me know replying to this thread.

  • This is a Flyback working in DCM, so the volt-second balance equation is the following:

    Vin*D=(Vout+Vf)*Nps*D2

    Where D2=1-D-D3 and D3 is the time where both devices are off.

    To calculate D value you need to also consider the charge balance of the capacitor. With both equations you will get this equation for D:

    D=(Vout+Vf)/Vin*swrt(2*fs*L/R)

    [bobo] you mean D=(Vout+Vf)/Vin*sqrt(2*fs*L/R) ? 

    In the case of EVM, R is R2 and R28 in parallel, which is 31 ohm?  What is L represent for and what is its value on the EVB?

  • Hi Bobo,

     1. you mean D=(Vout+Vf)/Vin*sqrt(2*fs*L/R) ? 

    Yes

    2. In the case of EVM, R is R2 and R28 in parallel, which is 31 ohm?  What is L represent for and what is its value on the EVB?

    R is the load resistor, whose value depends on how much power is delivered. In the case of the EVM, for 125V<Vin<1000V Pout=40W then R=Vout^2/Pout=5.625ohms. 

    L is the magnetizing inductance of the transformer seen at the primary side. For the EVM L=550uF

    If you have any further questions let me know replying to this thread.