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TPS3813K33-EP: RESET abnormal

Haury Zhou
Expert 8136 points

Part Number: TPS3813K33-EP
Other Parts Discussed in Thread: TPS3813

Hi team,

As the below sch, C_WDT=1nF, the typical time out is 408ms.

The period of MCU_WDI signal is 60ms. High level is 30ms and low level is 30ms.

But the /RESET is continued low level.

Could you help to check design and tell me why the /RESET is abnormal?

BRs

Haury

  • 0
    TI__Mastermind 23630 points

    Hi Haury,

    Could you please help check that the VDD is above 2.93V?

    If it is above 2.93V a scope shot of the RESET, VDD and WDR would be useful for debugging as well.

    Jesse 

  • 0 in reply to Jesse Villanueva
    TI__Genius 11845 points

    Hi Jesse 

     The VDD is above 2.93V.

    After disconnecting the reset signal to the MCU path, measure the VDD and /reset waveforms as follows, measure the WDI and /reset waveforms as follows. 30 ms between the rising edge of the first feeder signal high, why is reset caused?

    I calculated that their WDI period met the specification. Why does reset occur when WDI has a rising edge? What could be causing it? Can you give me some advice?
    There are other considerations besides the need for the WDI signal period to be greater than the tboundary,max？

     

    Best Regards!

    Mason

  • 0 in reply to Mason Chen
    TI__Mastermind 23630 points

    Hi Mason,

    Since this device is a window WD device, it looks like the device is hitting an early fault RESET assertion.  With their current setup the lower boundary window is at  15.8ms, so if they delay their initial pulse by another 10ms, the RESET should stop asserting initialization. Also the device only detects the rising edge of the WDI pulse.

    Jesse 

  • 0 in reply to Jesse Villanueva
    TI__Genius 11845 points

    Hi Jesse

    Thanks for your help. What is the early fault RESET assertion? I didn't find it in the Specifications. Could you tell me the detrital? My customer is concerned that this reset initialization will cause them an indeterminate risk and they want us to give a good theoretical basis. Similarly, I do not understand why an early fault reset assertion occurs. I hope I can answer my questions. Thanks a lot. 

    I still cannot understand the reset in the figure below. Can you give me some information about it?

    Best Regards!

    Mason

  • 0 in reply to Mason Chen
    TI__Mastermind 23630 points

    Mason,

    The TPS3813 is a window watchdog, which mean a fault can assert when a rising edge is detected before the lower boundary, which is an early fault, as well as a pulse not being detected by the time the upper boundary finishes, which is a late fault. In their setup the lower boundary. For their setup, WDR=0 WDT=1nF, the lower boundary is typ= 15.8ms min= 14.2ms and max = 17.3ms.

    From the image above, it looks like from the rising edge of the RESET and to the rising edge of the WDI is about ~13ms which is below the lower boundary of the window.

    Jesse 

  • 0 in reply to Jesse Villanueva
    TI__Genius 11845 points

    Hi Jesse

    Thanks for your help. Is it 1st Window Without Lower Boundary needs to be greater than tboundary,max? In other words, can no dogs be fed directly after RESET has just recovered? Is this requirement reasonable? 

     I also did not find the time requirements for the 1st Window Without Lower Boundary in the specification book.Can you tell me where this requirement is.

    Best Regards!

    Mason

  • +1 in reply to Mason Chen
    TI__Mastermind 23630 points

    Hi Mason,

    Yes that is correct, supposedly, on the first frame should not have a lower boundary. I want to troubleshoot the RESET assertion first by adjusting the rising edge input time on the WDI. I have ordered samples for this part so I can test the part on my  bench.

    Jesse