Hi Team,
Whether this Vaux voltage across 0V 3 times(when DRV turn-off) will cause to UVLO fault? I found some materials in TI.com, shown as Fig.1 and 2.
Customer find their system happened stop, and wavs is shown as Fig.3. Could you please help check this case? Thanks.
Fig. 1
Fig. 2
Fig. 3
Bule is VDD, green is CS, yellow is Vaux, red is Flyback output.
Hi Francis,
The aux winding itself goes below the UVLO threshold, but there is a diode and capacitor CVDD that holds up VDD during this phase:
To be clear UVLO is based on the voltage at the VDD pin, not VS.
I hope this answers your question.
Hi JCHK,
So why below condition device will stop? And could you please provide your professional advice why customer's condition will also cause to stop? Thanks.
BRs,
Francis
Hi JCHK,
Customer feedback the VDD and CS had been tested, VCC is VDD Pin and CS is CS Pin in below figure.
Fig. 3
