I'd like to check if we still can use DTX-3.3 LDO solution with following condition
Vin=12V Vout=3.3V Iout=0.1605A ambient=50C.
The power loss is around (12-3.3)*0.1605=1.4W. But I found the Power loss Figure 9-14 is almost on limitation.
Only Theta JA=47C can margin support.
So, I'd like to check if we still can we this solution. Any recommendation need?
Hey Jax,
The rise in junction temperature, of a board laid out in the JEDEC standard, will be:
TJ = TA + (PD*Theta-JA)
TJ = TA + (1.396W)(45.7C/W)
TJ = TA + 62.97C
TJ = 50C + 62.97C
TJ = 112.97C
The recommended operating conditions for this device are up to 125C.
You are still below that threshold and, typically, Theta-JA value are higher than what would be standard for a well-laid out board design.
A helpful paper to reference would be An empirical analysis of the impact of board layout on LDO thermal performance
Best,
Juliette
