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TPS6593-Q1: PFSM of PMIC: state of volatile registers after recovery

Wajdi Slama
Intellectual 480 points
Part Number: TPS6593-Q1

Hello support team,

let's assume we had an LDO out of range event ( OV or UV error). The PMIC in this case will trigger the PFSM to move to "Safe_Recovery" state.

Question-1: Does PMIC leaves this safe state once the voltage is back within the ranges, and moves back to "Mission States"?
Question-2: if yes,  are we still able to read the error events from INT_TOP ? 
                   
Regards,
Wajdi

  • 0
    TI__Mastermind 20388 points

    Hello Wajdi,

    team bandwidth at the moment is limited, please do understand. I'll circle back to this by EOD Friday.

    BR,

    Nicholas

  • 0 in reply to Nicholas McNamara
    TI__Mastermind 20388 points
    Wajdi Slama said:
    Question-1: Does PMIC leaves this safe state once the voltage is back within the ranges, and moves back to "Mission States"?

    If programmed to do an orderly shut down, it will go to the Safe_Recovery and try to make a recovery attempt. If the device is able to recovery from then it will move to the MIssion States. Either way it will increment the attempt counter and after the counter exceeds the defined threshold, the device will not attempt another recovery and will need to be power cycled in order to  attempt to function correctly again. The section in the user guide that explains this better is in 8.4.1.3.1 Power Rail Output Error.

    Wajdi Slama said:
    Question-2: if yes,  are we still able to read the error events from INT_TOP ? 

    Yes, you are able to.

    BR,

    Nicholas

  • 0 in reply to Nicholas McNamara
    Intellectual 480 points

    Hello Nicholas, 

    can you confirm that the "Boot Bist" state will not erase any error flags ( coming from INIT state). 

    BR,

    Wajdi

  • +1 in reply to Wajdi Slama
    TI__Mastermind 20388 points

    Hello Wajdi,

    the error flags (interrupts) will not be erased. As there will be interrupts still in the registers they correspond to, for example if the attempted recoveries exceed the threshold, this will be saved in their respective interrupt registers.

    Or if a short circuit occurs on a mission critical rail and successfully recovers from SAFE_RECOVERY:

    SC FAILURE ON BUCKX -> SAFE_RECOVERY -> INIT -> BOOT_BIST -> MISSION STATES

    As seen on the diagram below

    BR,

    Nicholas