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TPS6593-Q1: DISABLE_WDOG as functionality in GPIO8

Wajdi Slama
Intellectual 480 points
Part Number: TPS6593-Q1
Other Parts Discussed in Thread: TPS6594-Q1

Hello support team, 

we would like to better understand the functionality of "DISABLE_WDOG" ( currently assigned to GPIO8 in our PMIC configuration): 

let is assume the wdg is per default disabled. At each startup the MCU sends an SPI sequence to PMIC to enable the QnA watchdog, and starts serving it.

Now during run time we pull GPIO8 to request "DISABLE_WDOG",:

- Question-1: Does this action  disable QnA mode, disable WD_EN bit or the reset reaction ? we assume that the MCU keeps serving the QnA after pulling GPIO8 ( unaware of the pulling action).


- Qeustion-2: if the answer is NO ( no effect, QnA keeps running), then what if we reset the Ecu, and pull GPIO8 while QnA still disabled. Once MCU is powered up, will it manage to activate the QnA in this case ?

Best regards,

Wajdi

  • 0
    TI__Mastermind 20307 points

    Hello Wajdi,

    before I can begin to answer your questions, do you have a part number associated with your question.

    That helps a great deal on being able to answer these, thank you.

    Best regards,

    Nicholas

  • 0 in reply to Nicholas McNamara
    Intellectual 480 points

    Hello Nicholas,

    Prototype OPN:       PTPS6593C412RWERQ1
    RTM Device OPN: TPS6593C412RWERQ1

  • 0 in reply to Wajdi Slama
    TI__Mastermind 20307 points

    Thank you Wajdi,

    that part number gives me a lot more context in better answer this question, please allow some time to best respond.

    Thank you

  • 0 in reply to Nicholas McNamara
    Intellectual 480 points

    Hello Nicholas, 

    any updates regarding this ticket ?

  • +1 in reply to Wajdi Slama
    TI__Mastermind 20307 points

    Hello Wajdi,

    Wajdi Slama said:

    - Question-1: Does this action  disable QnA mode, disable WD_EN bit or the reset reaction ? we assume that the MCU keeps serving the QnA after pulling GPIO8 ( unaware of the pulling action).

    according this section of the datasheet:

    The watchdog in the TPS6594-Q1 device has a Watchdog Disable function to prevent an unwanted MCU
    reset in case the MCU is un-programmed or needs to be reprogrammed. In order to activate this Watchdog
    Disable function for an un-programmed MCU, DISABLE_WDOG pin must be asserted to a logic-high level for
    a time-interval longer than tWD_DIS prior to the moment the device releases the nRSTOUT pin. If the Watchdog
    Disable function is activated in this way, the device sets bit WD_PWRHOLD to keep the watchdog in the Long
    Window. The watchdog stays in the Long Window until the MCU clears the WD_PWRHOLD bit.

    When disabled as a pin it does not "disable" the watchdog, it is still enabled, but will be in the long window until the PW_PWRHOLD bit is set to '0'

    The hardware on the pin will enable this feature and to return interface writes to the respective register fields will need to be done.

    This effectively, provides the same thing as disabling the watchdog. As it will be configurable and will not serve requests at the time.

    Here is the time from the datasheet to know the setup time for the GPIO8 disable watchdog function:

    Sorry for the delay, but I hope this helps in the understanding of the GPIO8's disable watchdog function.

    BR,

    Nicholas