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LM5152-Q1: Is there any "charge pump disabled comdition" during "CP" pin is higher than 2V?

Part Number: LM5152-Q1

HI team, 

Is there any "charge pump disabled comdition" during "CP" pin is higher than 2V? 

Datasheet says there are several modes. I understood that as lowers, could you confirm if my understanding is correct? Is there any ohter conditions we need to consider?

(1) If we do not consider "Shutdown Mode" and "Configuration Mode" and CP pin is higher than 2V, there is no mode with charge pump off. This is the same even if VEN is less than VH. 

(2) Shutdown mode disables charge pump. But LM5152-Q1 does not enter this mode @CP pin is higher than 2V once it is in active mode. 

(3) Configuration Mode disables charge pump. But this mode is just after enabling; transition from shutdown mode.

(4) Active mode enables charge pump.

(5) Sleep mode enables charge pump if CP pin is higher than 2V. This mode starts just afte for 16 consecutive skip cycles on active mode

(6) Deep Sleep Mode enables charge pump if CP pin is higher than 2V

Regards,
Ochi

  • Hi Ochi,

    I will try my best to answer your questions:

    1. In the datasheet it states that for CP enable to be active or enabled the pin has to be greater than 2V, apart from shutdown mode where the device is basically off the charge pump should be off, maybe during the configuration mode as well.

    2. In shutdown mode yes it should be disabled. As for the not entering the shutdown mode once in active mode and CP pin is higher than 2V I am not sure, from where did you interpret that?

    3. yes configuration mode is the transition from shutdown to active mode.

    4. yes correct.

    5. The device enters the sleep mode if low side driver skips 16 consecutive cycles on active mode and yes charge pump enabled through that CP pin voltage above 2V.

    6. Yes correct, the charge pump will be enabled when the CP pin is greater than 2V.

    BR,

    Haroon

    All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults” and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml).

  • Hi Haroon, 

    Thank you so much for your instruction. Could you confirm one more question as lower?

    2. In shutdown mode yes it should be disabled. As for the not entering the shutdown mode once in active mode and CP pin is higher than 2V I am not sure, from where did you interpret that?

    I referred to lower (A) and (B) sentences in the datasheet. " 

    (A) From Table 7-1. Pin Functions, SYNC/DITHER/VH/CP, "Charge pump enable pin. If the pin is greater than 2.0 V, the internal charge pump maintains the HB pin voltage above its HB UVLO threshold for bypass operation, which allows the high-side switch to turn on 100% during bypass operation (LM5152-Q1 only)."

    (B) From 9.4.1.1 Shutdown Mode, "When EN is less than VEN and VH is less than VSYNC, the device shuts down, consuming 3 μA from BIAS. In shutdown mode, COMP, SS, and STATUS are grounded."

    Considering (A) and (B), I understood that "Shutdown mode disables charge pump. But LM5152-Q1 does not enter this mode @CP pin is higher than 2V once it is in active mode." or "Shutdown mode disables charge pump. But LM5152-Q1 does not enter this mode @CP pin is higher than VSYNC-FALLING=0.4V once it is in active mode". Could you confirm if any misunderstanding?

    1. In the datasheet it states that for CP enable to be active or enabled the pin has to be greater than 2V, apart from shutdown mode where the device is basically off the charge pump should be off, maybe during the configuration mode as well.

    I understood! Thank you. 

    Regards,
    Ochi 

  • Hi Ochi,

    Please allow me to confirm this with my peers and experts. I will get back to you

    BR,

    Haroon

  • Hi Ochi,

    Thank you for your patience, yes from the two sentences you have stated above it can be inferred what you are saying, as long as the CP enable pin is above the 2V mark as it is stated there. it does not mention the Vsync falling threshold.

    Hope this helps,

    BR,

    Haroon

    All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults” and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml).

  • Hi Ochi,

    I will close this thread now, If you have further questions just reply on this thread.

    BR,

    Haroon

  • Hi Haroon, 

    Does this device enter configuration mode if "SYNC/DITHER/VH/CP">2V and "UVLO/EN" is lower than VEN? Then, how much gate soruce voltage of high side switch is?

    "Table 7-1. Pin Functions" syas "VCC hold pin. If the pin is greater than 2.0 V, the device holds the VCC pin voltage when the EN pin is grounded, which helps to restart quickly without reconfiguration."

    Regards,
    Ochi

  • Hi Ochi,

    I will get back to you as soon as possible.

    Please give me some time.

    BR,

    Haroon

  • Hi Ochi,

    Sorry for the delayed response, regarding your query configuration mode the device is enabled initially, so no VEN is not lower than VEN.

    Vgs when the SYNC pin is >2V and EN pin is lower than VEN?

    BR,

    Haroon

  • Hi Haroon,

    regarding your query configuration mode the device is enabled initially, so no VEN is not lower than VEN.

    What do you mean for "no VEN is not lower than VEN?

    Vgs when the SYNC pin is >2V and EN pin is lower than VEN?

    Apologize not for understanding, but could you answer in simple? Whether entering configuration mode or not, and how much Vgs is in lower condition?

    I copied the question: "Does this device enter configuration mode in the case "SYNC/DITHER/VH/CP">2V and "UVLO/EN"<VEN(threshold)? Then, how much gate soruce voltage of high side switch is?" 

    Regards,
    Ochi

  • Hi Ochi,

    Sorry for the confusion.

    What do you mean for "no VEN is not lower than VEN?

    Yes I was wrong during configuration mode the device is enabled initially, so EV/UVLO pin goes above VEN, the configuration duration is around 120us and after that the device goes into active mode.

    as for the second part of the question, I hope I got your question right, you mean during this configuration mode what is the Vgs of the LS FET? Well according to the datasheet, it says that in active mode only the Soft-start starts and the device starts switching, so it can be inferred that during the configuration mode the FETs are off, so I would say Vgs should be zero, although I am not sure, maybe if you have the EVM you could try and measure? it is not stated in the datasheet, I can only infer this from what is written in the datasheet. May I ask why are you asking this?

    BR,

    Haroon

  • Hi Harron, 

    Thnak you. As I evaluated EVM, if EN/UVLO=low, its high side Vgs was 0V regardless of SYNC/DITHER/VH/CP pin voltage. I understood that EN/UVLO=high needs to be high for bypass operation. 

    Regards,
    Ochi

  • Hi Ochi,

    Yes UVLO/EN has to cross the threshold in order for the device to start switching, so if the pin is low the device is not turned on.

    Hope this helps.

    BR,

    Haroon