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TPS62933: PSpice: different max step size value has the different simulation result

Steven Wang
Prodigy 230 points
Part Number: TPS62933

Hi, 

I'm using Pspice for TI + TPS62933 PSpice Transient Model to simulte the circuit. According to the example design, Vin=24V, Output=5V 3A. The buck IC operates at around 500kHz (2us period). In the PSpice simulation profile, if I increase "max step size" value, the simulation result will be incorrect after a certain max step size threshold. 

run to time=200us for all trails

Trail 1: max step size=5ns

Trial 2: max step size=20ns

Trail 3: max step size=40ns

Trail 4: max step size=50ns

  • 0
    TI__Genius 16632 points

    Hello Steven,

    This is known thing that using larger simulation step size could cause wrong simulation results. Please do not change the default simulation setting. Or you could use smaller step size. 

  • 0 in reply to Miranda Gu
    Prodigy 230 points

    Hi Miranda, 

    Why large max step size will lead to the incorrect result? 

    Is there a rule of thumb to select the appropriate max step size for all general circuit? If max step size is too large, the result be will incorrect. If max step size is too small, the simulation will take a long time. Do we have to start from small step size and make trails? 

    Thanks 

  • +1 in reply to Steven Wang
    TI__Genius 16632 points

    Hello Steven,

    It's always an important thing to get a proper max-step-size during pspice model development. Too big max-step-size could cause simulation results inaccurate. Too small max-step-size could cause very long simulation time. Actually the simulation setting we posted on ti.com is fairly proper value after our many tests. So please use our example max-step-size value first. P.S. In my experience, I will set about 1ns~100ns, if results looking bad, I will decrease the value then check again.