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TPS62933: PSpice has the inconsistent simulation result with Webench

Steven Wang
Prodigy 230 points
Part Number: TPS62933

Hi, my goal is to design a buck circuit with TPS62933. Input=24VDC, Output=10V 3A. 

Design: Use Wenech to design the circuit

Simulation: Use Pspice for TI + TPS62933 PSpice Transient Model to validate the above circuit. According to the webench design, I did the following modifications to the example PSpice circuit (see red box). The simulation result is given below. 

Questions

1) Why V(SW) is graduallt decreasing? It should be a 0 or 24V switching signals. As a result, I(RLOAD) and V(VOUT) are NOT 10V 3A. 

2) See blue box, why 24V with two 49.9kOhm voltage divider makes EN pin = 5V? It should be 12V by resistor votlage divider. 

3) At the output load, why the simulation result decreeases to 0V, but label still shows 5V? 

Thank you very much

  • +1
    TI__Genius 16632 points

    Hello Steven,

    Seems you are running steadystate simulation, which sets initial voltages of external components like Cout, in order to make the simulation quicker reach to steadystate operation. That's why you see some voltages at first.

    Please run startup simulation instead, which does not have initial voltage. P.S. but the simulation time is much longer than steadystate simulation.

  • 0 in reply to Miranda Gu
    Prodigy 230 points

    Hi Miranda,

    If I use STEADY STATE simulation, does that mean my simulation profile must to be configured after the steady state is reached? For example, if I set soft start time = 5ms, 

    Run to time: >5ms, such as 10ms

    Save data after: >5ms, such as 8ms

    Max step size: a reasonable value, such as 1us

    Correct? If I choose save data after = 3ms (before steady state is reached), the simulation result could be incorrect? 

    Thanks 

  • 0 in reply to Steven Wang
    TI__Genius 16632 points

    Hello Steven,

    The setting time (how long it takes until Vout becomes stable right value) of steadystate simulation is unknow. P.S. During model development, we set a save-data-time value based on simulation results, but it's unknown if you haven't run the model.

    The soft-start time you set is useless in steadystate simulation.

    Please use startup simulation if you wonder startup process waveforms.