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TPS929240-Q1: Current Register Update issue

mustafa fathy
Prodigy 81 points
Part Number: TPS929240-Q1

Hello,

We have issue with updating Current register during run time in case of applying this test  (doing Software and Hardware reset more than one time).

Our current software implementation is sending the following frames (unlocking sequence) for one time during initialization:

    1- Broadcast Write frame to CLR register with address <0x91> and data value <0x07>.

    2- Broadcast Write frame to CTRLGATE register with address <0x96> and data value <0x43>.

    3- Broadcast Write frame to CTRLGATE register with address <0x96> and data value <0x4F>.

    4- Broadcast Write frame to CTRLGATE register with address <0x96> and data value <0x44>.

    5- Broadcast Write frame to CTRLGATE register with address <0x96> and data value <0x45>.

    6- Broadcast Write frame to LOCK register with address <0x93> and data value <0x00>.

    7- Broadcast Write frame to EN0 register with address <0x90> and data value <0x77 , 0x77 , 0x77, 0x77>.

Before applying test we can update current register but after we can't.

Here it's our investigation:

    1- We tried to read Current register after updating it but as we see below current register not updated 

   2- We tried to send the each unlocking pervious frame with interframe delay (20ms) but the same issue.

   3- We tried to send the unlocking frames periodically and issue is resolved and we managed to read current register as attached below 

So please we need to know the best practice to send unlocking sequence to resolve the issue even if we apply the test  because of sending them periodically, will impact bus load.

  • +1
    TI__Genius 17520 points

    I think the sequence should be ok. 

    Please try writing one extra dummy sequence at the beginning to ensure the start status of CTRLGATE is locked at beginning. For example:  0x00, 0x43, 0x4F, 0x44, 0x45

    I hope it can solve the issue. If not, please check below some thoughts/question: 

    1. Does the issue only happens under this case or it also fails when doing other read/write operation? 

    2. Per my understanding, sometimes it works since the issue can be resolved by sending the unlocking frames periodically. Is it right? What is the baud rate? If it can be improved by reducing baud rate by 25% or 50%( for a try) ? 

    3. Can you offer original digital analyzer data? Are these data captured on TPS929240 RX/TX pin? If possible, oscilloscope waveform on device TX/RX pin is also highly appreciated. The below shows that there is resonant for read back data, I would like to check details. 

     

  • 0 in reply to Xiaoguang
    Prodigy 81 points

    Hello Xiaoguang,

    I have tried to send this dummy frame (lock CTRLGATE) before sending unlocking sequence during init state and it success.

    Thank you for your support